Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 5 | #include <cpu/x86/lapic.h> |
| 6 | #include <cpu/x86/mp.h> |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 7 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 8 | #include <cpu/intel/smm_reloc.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 9 | #include <cpu/intel/turbo.h> |
| 10 | #include <intelblocks/cpulib.h> |
| 11 | #include <intelblocks/mp_init.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 12 | #include <soc/cpu.h> |
| 13 | #include <soc/msr.h> |
| 14 | #include <soc/pci_devs.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 15 | #include <soc/systemagent.h> |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 16 | #include <cpu/x86/mtrr.h> |
| 17 | #include <cpu/intel/microcode.h> |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 18 | #include <cpu/intel/common/common.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 19 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 20 | #include "chip.h" |
| 21 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 22 | static void soc_fsp_load(void) |
| 23 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 24 | fsps_load(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 27 | static void configure_misc(void) |
| 28 | { |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 29 | msr_t msr; |
| 30 | |
Angel Pons | bda02b0 | 2020-09-28 01:10:40 +0200 | [diff] [blame] | 31 | config_t *conf = config_of_soc(); |
| 32 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 33 | msr = rdmsr(IA32_MISC_ENABLE); |
| 34 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 35 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Matt Delco | 54e9894 | 2020-03-09 12:41:09 -0700 | [diff] [blame] | 36 | wrmsr(IA32_MISC_ENABLE, msr); |
| 37 | |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 38 | /* Set EIST status */ |
| 39 | cpu_set_eist(conf->eist_enable); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 40 | |
| 41 | /* Disable Thermal interrupts */ |
| 42 | msr.lo = 0; |
| 43 | msr.hi = 0; |
| 44 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 45 | |
| 46 | /* Enable package critical interrupt only */ |
| 47 | msr.lo = 1 << 4; |
| 48 | msr.hi = 0; |
| 49 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 50 | |
| 51 | /* Enable PROCHOT */ |
| 52 | msr = rdmsr(MSR_POWER_CTL); |
| 53 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 54 | msr.lo |= (1 << 23); /* Lock it */ |
| 55 | wrmsr(MSR_POWER_CTL, msr); |
| 56 | } |
| 57 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 58 | static void configure_c_states(void) |
| 59 | { |
| 60 | msr_t msr; |
| 61 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 62 | /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ |
| 63 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 64 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 65 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
| 66 | |
| 67 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ |
| 68 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 69 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 70 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
| 71 | |
| 72 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 73 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 74 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 75 | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 76 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
| 77 | |
| 78 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 79 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 80 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 81 | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 82 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 83 | |
| 84 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 85 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 86 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 87 | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 88 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 89 | } |
| 90 | |
| 91 | /* All CPUs including BSP will run the following function. */ |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 92 | void soc_core_init(struct device *cpu) |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 93 | { |
| 94 | /* Clear out pending MCEs */ |
Pratik Prajapati | 2ad1ddb | 2017-08-28 12:28:24 -0700 | [diff] [blame] | 95 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 96 | * of these banks are core vs package scope. For now every CPU clears |
| 97 | * every bank. */ |
Subrata Banik | f91344c | 2019-05-06 19:23:26 +0530 | [diff] [blame] | 98 | mca_configure(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 99 | |
| 100 | /* Enable the local CPU apics */ |
| 101 | enable_lapic_tpr(); |
| 102 | setup_lapic(); |
| 103 | |
| 104 | /* Configure c-state interrupt response time */ |
| 105 | configure_c_states(); |
| 106 | |
| 107 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 108 | configure_misc(); |
| 109 | |
Michael Niewöhner | 5611cfd | 2020-10-11 13:04:02 +0200 | [diff] [blame] | 110 | set_aesni_lock(); |
| 111 | |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 112 | enable_pm_timer_emulation(); |
| 113 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 114 | /* Enable Direct Cache Access */ |
| 115 | configure_dca_cap(); |
| 116 | |
| 117 | /* Set energy policy */ |
| 118 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 119 | |
| 120 | /* Enable Turbo */ |
| 121 | enable_turbo(); |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 122 | |
| 123 | /* Enable Vmx */ |
| 124 | set_vmx_and_lock(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 125 | } |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 126 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 127 | static void per_cpu_smm_trigger(void) |
| 128 | { |
| 129 | /* Relocate the SMM handler. */ |
| 130 | smm_relocate(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 133 | static void post_mp_init(void) |
| 134 | { |
| 135 | /* Set Max Ratio */ |
| 136 | cpu_set_max_ratio(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 140 | * start flowing. |
| 141 | */ |
Kyösti Mälkki | 040c531 | 2020-05-31 20:03:11 +0300 | [diff] [blame] | 142 | global_smi_enable_no_pwrbtn(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 143 | |
| 144 | /* Lock down the SMRAM space. */ |
| 145 | smm_lock(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | static const struct mp_ops mp_ops = { |
| 149 | /* |
| 150 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 151 | * that are set prior to ramstage. |
| 152 | * Real MTRRs programming are being done after resource allocation. |
| 153 | */ |
| 154 | .pre_mp_init = soc_fsp_load, |
| 155 | .get_cpu_count = get_cpu_count, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 156 | .get_smm_info = smm_info, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 157 | .get_microcode_info = get_microcode_info, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 158 | .pre_mp_smm_init = smm_initialize, |
| 159 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 160 | .relocation_handler = smm_relocation_handler, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 161 | .post_mp_init = post_mp_init, |
| 162 | }; |
| 163 | |
| 164 | void soc_init_cpus(struct bus *cpu_bus) |
| 165 | { |
| 166 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 167 | printk(BIOS_ERR, "MP initialization failure.\n"); |
John Su | 3126964 | 2019-01-10 14:53:26 +0800 | [diff] [blame] | 168 | |
| 169 | /* Thermal throttle activation offset */ |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 170 | configure_tcc_thermal_target(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 171 | } |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 172 | |
| 173 | int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |
| 174 | { |
| 175 | msr_t msr1; |
| 176 | msr_t msr2; |
| 177 | |
| 178 | /* |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 179 | * If PRMRR/SGX is supported the FIT microcode load will set the msr |
| 180 | * 0x08b with the Patch revision id one less than the id in the |
| 181 | * microcode binary. The PRMRR support is indicated in the MSR |
| 182 | * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the |
| 183 | * same microcode during CPU initialization. If SGX is enabled, as |
| 184 | * part of SGX BIOS initialization steps, the same microcode needs to |
| 185 | * be reloaded after the core PRMRR MSRs are programmed. |
| 186 | */ |
| 187 | msr1 = rdmsr(MTRR_CAP_MSR); |
| 188 | msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); |
| 189 | if (msr2.lo && (current_patch_id == new_patch_id - 1)) |
| 190 | return 0; |
| 191 | |
Kyösti Mälkki | eadd251 | 2020-06-11 09:52:45 +0300 | [diff] [blame] | 192 | return (msr1.lo & MTRR_CAP_PRMRR) && |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 193 | (current_patch_id == new_patch_id - 1); |
| 194 | } |