Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 17 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 19 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 21 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Elyes HAOUAS | ece7d0c | 2018-07-03 18:34:10 +0200 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <cpu/intel/romstage.h> |
| 25 | #include <cpu/x86/bist.h> |
| 26 | #include <cpu/x86/lapic.h> |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
Edward O'Callaghan | 2c9e370 | 2014-05-21 06:51:15 +1000 | [diff] [blame] | 29 | #include <northbridge/intel/i945/i945.h> |
| 30 | #include <northbridge/intel/i945/raminit.h> |
| 31 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Elyes HAOUAS | ece7d0c | 2018-07-03 18:34:10 +0200 | [diff] [blame] | 32 | #include <superio/winbond/common/winbond.h> |
| 33 | #include <superio/winbond/w83627ehg/w83627ehg.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 34 | #include <southbridge/intel/common/pmclib.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 35 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 36 | #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 37 | #define SUPERIO_DEV PNP_DEV(0x4e, 0) |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 38 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 39 | static void ich7_enable_lpc(void) |
| 40 | { |
| 41 | // Enable Serial IRQ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 42 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 43 | // Set COM1/COM2 decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 44 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 45 | // Enable COM1/COM2/KBD/SuperIO1+2 |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 46 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN |
| 47 | | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN |
| 48 | | COMB_LPC_EN); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 49 | // Enable HWM at 0x290 |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 50 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 51 | // io 0x300 decode |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 52 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | /* This box has one superio |
| 56 | * Also set up the GPIOs from the beginning. This is the "no schematic |
| 57 | * but safe anyways" method. |
| 58 | */ |
| 59 | static void early_superio_config_w83627ehg(void) |
| 60 | { |
Antonello Dettori | cca5938 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 61 | pnp_devfn_t dev; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 62 | |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 63 | dev = SUPERIO_DEV; |
Keith Hui | bb73c98 | 2017-08-13 16:31:18 -0400 | [diff] [blame] | 64 | pnp_enter_conf_state(dev); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 65 | |
Elyes HAOUAS | 2e97780 | 2018-02-16 08:27:50 +0100 | [diff] [blame] | 66 | pnp_write_config(dev, 0x24, 0xc4); // PNPCVS |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 67 | |
| 68 | pnp_write_config(dev, 0x29, 0x01); // GPIO settings |
| 69 | pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 |
| 70 | pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? |
| 71 | pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? |
| 72 | pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? |
| 73 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 74 | dev = PNP_DEV(0x4e, W83627EHG_SP1); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 75 | pnp_set_logical_device(dev); |
| 76 | pnp_set_enable(dev, 0); |
| 77 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 78 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 79 | pnp_set_enable(dev, 1); |
| 80 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 81 | dev = PNP_DEV(0x4e, W83627EHG_SP2); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 82 | pnp_set_logical_device(dev); |
| 83 | pnp_set_enable(dev, 0); |
| 84 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 85 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
| 86 | // pnp_write_config(dev, 0xf1, 4); // IRMODE0 |
| 87 | pnp_set_enable(dev, 1); |
| 88 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 89 | dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 90 | pnp_set_logical_device(dev); |
| 91 | pnp_set_enable(dev, 0); |
| 92 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 93 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
| 94 | //pnp_write_config(dev, 0xf0, 0x82); |
| 95 | pnp_set_enable(dev, 1); |
| 96 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 97 | dev = PNP_DEV(0x4e, W83627EHG_GPIO2); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 98 | pnp_set_logical_device(dev); |
| 99 | pnp_set_enable(dev, 1); // Just enable it |
| 100 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 101 | dev = PNP_DEV(0x4e, W83627EHG_GPIO3); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 102 | pnp_set_logical_device(dev); |
| 103 | pnp_set_enable(dev, 0); |
| 104 | pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output |
| 105 | pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 |
| 106 | pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient |
| 107 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 108 | dev = PNP_DEV(0x4e, W83627EHG_FDC); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 109 | pnp_set_logical_device(dev); |
| 110 | pnp_set_enable(dev, 0); |
| 111 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 112 | dev = PNP_DEV(0x4e, W83627EHG_PP); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 113 | pnp_set_logical_device(dev); |
| 114 | pnp_set_enable(dev, 0); |
| 115 | |
| 116 | /* Enable HWM */ |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 117 | dev = PNP_DEV(0x4e, W83627EHG_HWM); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 118 | pnp_set_logical_device(dev); |
| 119 | pnp_set_enable(dev, 0); |
| 120 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 121 | pnp_set_enable(dev, 1); |
| 122 | |
Keith Hui | bb73c98 | 2017-08-13 16:31:18 -0400 | [diff] [blame] | 123 | pnp_exit_conf_state(dev); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static void rcba_config(void) |
| 127 | { |
| 128 | /* Set up virtual channel 0 */ |
| 129 | //RCBA32(0x0014) = 0x80000001; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 130 | |
| 131 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 132 | RCBA32(D31IP) = 0x00042210; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 133 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 134 | RCBA32(D28IP) = 0x00214321; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 135 | |
| 136 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 137 | RCBA16(D31IR) = 0x0132; |
| 138 | RCBA16(D30IR) = 0x0146; |
| 139 | RCBA16(D29IR) = 0x0237; |
| 140 | RCBA16(D28IR) = 0x3201; |
| 141 | RCBA16(D27IR) = 0x0146; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 142 | |
| 143 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 144 | RCBA8(OIC) = 0x03; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 145 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 146 | /* Enable PCIe Root Port Clock Gate */ |
| 147 | // RCBA32(0x341c) = 0x00000001; |
| 148 | } |
| 149 | |
| 150 | static void early_ich7_init(void) |
| 151 | { |
| 152 | uint8_t reg8; |
| 153 | uint32_t reg32; |
| 154 | |
| 155 | // program secondary mlt XXX byte? |
| 156 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 157 | |
| 158 | // reset rtc power status |
| 159 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 160 | reg8 &= ~(1 << 2); |
| 161 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 162 | |
| 163 | // usb transient disconnect |
| 164 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 165 | reg8 |= (3 << 0); |
| 166 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 167 | |
| 168 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 169 | reg32 |= (1 << 29) | (1 << 17); |
| 170 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 171 | |
| 172 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 173 | reg32 |= (1 << 31) | (1 << 27); |
| 174 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 175 | |
| 176 | RCBA32(0x0088) = 0x0011d000; |
| 177 | RCBA16(0x01fc) = 0x060f; |
| 178 | RCBA32(0x01f4) = 0x86000040; |
| 179 | RCBA32(0x0214) = 0x10030549; |
| 180 | RCBA32(0x0218) = 0x00020504; |
| 181 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 182 | reg32 = RCBA32(GCS); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 183 | reg32 |= (1 << 6); |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 184 | RCBA32(GCS) = reg32; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 185 | reg32 = RCBA32(0x3430); |
| 186 | reg32 &= ~(3 << 0); |
| 187 | reg32 |= (1 << 0); |
| 188 | RCBA32(0x3430) = reg32; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 189 | RCBA16(0x0200) = 0x2008; |
| 190 | RCBA8(0x2027) = 0x0d; |
| 191 | RCBA16(0x3e08) |= (1 << 7); |
| 192 | RCBA16(0x3e48) |= (1 << 7); |
| 193 | RCBA32(0x3e0e) |= (1 << 7); |
| 194 | RCBA32(0x3e4e) |= (1 << 7); |
| 195 | |
| 196 | // next step only on ich7m b0 and later: |
| 197 | reg32 = RCBA32(0x2034); |
| 198 | reg32 &= ~(0x0f << 16); |
| 199 | reg32 |= (5 << 16); |
| 200 | RCBA32(0x2034) = reg32; |
| 201 | } |
| 202 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 203 | void mainboard_romstage_entry(unsigned long bist) |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 204 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 205 | int s3resume = 0; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 206 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 207 | if (bist == 0) |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 208 | enable_lapic(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 209 | |
| 210 | ich7_enable_lpc(); |
| 211 | early_superio_config_w83627ehg(); |
| 212 | |
| 213 | /* Set up the console */ |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 214 | console_init(); |
| 215 | |
| 216 | /* Halt if there was a built in self test failure */ |
| 217 | report_bist_failure(bist); |
| 218 | |
| 219 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 220 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 221 | system_reset(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | /* Perform some early chipset initialization required |
| 225 | * before RAM initialization can work |
| 226 | */ |
| 227 | i945_early_initialization(); |
| 228 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 229 | s3resume = southbridge_detect_s3_resume(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 230 | |
| 231 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 232 | enable_smbus(); |
| 233 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 234 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 235 | dump_spd_registers(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 236 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 237 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 238 | |
| 239 | /* Perform some initialization that must run before stage2 */ |
| 240 | early_ich7_init(); |
| 241 | |
| 242 | /* This should probably go away. Until now it is required |
| 243 | * and mainboard specific |
| 244 | */ |
| 245 | rcba_config(); |
| 246 | |
| 247 | /* Chipset Errata! */ |
| 248 | fixup_i945_errata(); |
| 249 | |
| 250 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 251 | i945_late_initialization(s3resume); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 252 | } |