Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <drivers/vpd/vpd.h> |
| 5 | #include <drivers/ocp/include/vpd.h> |
| 6 | #include <drivers/ipmi/ipmi_if.h> |
| 7 | #include <drivers/ipmi/ocp/ipmi_ocp.h> |
| 8 | #include <drivers/ocp/ewl/ocp_ewl.h> |
| 9 | #include <soc/romstage.h> |
| 10 | #include <defs_cxl.h> |
| 11 | #include <defs_iio.h> |
| 12 | #include <sprsp_ac_iio.h> |
Arthur Heymans | fff762e | 2024-03-28 14:42:50 +0100 | [diff] [blame] | 13 | #include <stdint.h> |
Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 14 | |
| 15 | #include "ipmi.h" |
| 16 | |
| 17 | void mainboard_ewl_check(void) |
| 18 | { |
| 19 | /* Enhanced Warning Log prints EWL type 3 primarily associated with MRC training failures */ |
| 20 | get_ewl(); |
| 21 | } |
| 22 | |
| 23 | static void mainboard_config_iio(FSPM_UPD *mupd) |
| 24 | { |
| 25 | int port; |
| 26 | |
| 27 | UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = |
Arthur Heymans | fff762e | 2024-03-28 14:42:50 +0100 | [diff] [blame] | 28 | (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; |
Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 29 | |
| 30 | /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ |
| 31 | for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) { |
| 32 | PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP; |
| 33 | PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP; |
| 34 | PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable; |
| 35 | PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE; |
| 36 | PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload; |
| 37 | PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed; |
| 38 | PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3; |
| 39 | } |
| 40 | /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ |
| 41 | for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) { |
| 42 | PciePortConfig[0].PEXPHIDE[port] = 1; |
| 43 | PciePortConfig[0].HidePEXPMenu[port] = 1; |
| 44 | } |
| 45 | PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; |
| 46 | PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; |
| 47 | PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; |
| 48 | PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_xxx8xxx8; |
| 49 | PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_xxxxxx16; |
| 50 | |
| 51 | PciePortConfig[0].PcieGlobalAspm = 0x1; |
| 52 | PciePortConfig[0].PcieMaxReadRequestSize = 0x5; |
| 53 | |
| 54 | /* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ |
| 55 | for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) { |
| 56 | PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP; |
| 57 | PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP; |
| 58 | PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable; |
| 59 | PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE; |
| 60 | PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload; |
| 61 | PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed; |
| 62 | PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3; |
| 63 | } |
| 64 | /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ |
| 65 | for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) { |
| 66 | PciePortConfig[1].PEXPHIDE[port] = 1; |
| 67 | PciePortConfig[1].HidePEXPMenu[port] = 1; |
| 68 | } |
| 69 | PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_x4x4x4x4; |
| 70 | PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; |
| 71 | PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; |
| 72 | PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_xxxxxx16; |
| 73 | PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_xxx8xxx8; |
| 74 | |
| 75 | PciePortConfig[1].PcieGlobalAspm = 0x1; |
| 76 | PciePortConfig[1].PcieMaxReadRequestSize = 0x5; |
| 77 | |
| 78 | /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ |
| 79 | if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { |
| 80 | printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); |
| 81 | } else { |
| 82 | /* Set socket 0 IIO PCIe PE1 to CXL mode */ |
| 83 | /* Set socket 1 IIO PCIe PE0 to CXL mode */ |
| 84 | /* eg. Protocl Auto Negotiation */ |
| 85 | mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL; |
| 86 | mupd->FspmConfig.IioPcieSubSystemMode0[1] = IIO_MODE_CXL; |
| 87 | |
| 88 | /* Disable CXL header bypass */ |
| 89 | mupd->FspmConfig.DfxCxlHeaderBypass = 0; |
| 90 | |
| 91 | /* Set DFX CXL security level to fully trusted */ |
| 92 | mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; |
| 93 | |
| 94 | /* Set DelayAfterPCIeLinkTraining to 2000 ms */ |
| 95 | mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 100 | { |
Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 101 | /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ |
| 102 | if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { |
| 103 | init_frb2_wdt(); |
| 104 | } |
| 105 | |
Shuo Liu | 45a670d | 2024-04-26 06:15:35 +0800 | [diff] [blame^] | 106 | /* Setup FSP log */ |
| 107 | mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, |
| 108 | FSP_LOG_DEFAULT); |
| 109 | if (mupd->FspmConfig.SerialIoUartDebugEnable) { |
| 110 | mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( |
| 111 | FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); |
| 112 | /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ |
| 113 | if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { |
| 114 | printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); |
| 115 | mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; |
| 116 | } |
Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 117 | } |
| 118 | |
Shuo Liu | 45a670d | 2024-04-26 06:15:35 +0800 | [diff] [blame^] | 119 | /* FSP Dfx PMIC Secure mode */ |
| 120 | mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( |
| 121 | FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); |
| 122 | |
Annie Chen | d31cbc7 | 2023-06-02 09:57:28 +0800 | [diff] [blame] | 123 | /* Set Rank Margin Tool to disable. */ |
| 124 | mupd->FspmConfig.EnableRMT = 0x0; |
| 125 | /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */ |
| 126 | /* Disable - Disables this feature */ |
| 127 | /*Auto - Sets it to the MRC default setting */ |
| 128 | mupd->FspmConfig.AttemptFastBoot = 0x1; |
| 129 | /* Set Attempt Fast Cold Boot to enable */ |
| 130 | /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on cold boots */ |
| 131 | /* Disable - Disables this feature */ |
| 132 | /* Auto - Sets it to the MRC default setting */ |
| 133 | mupd->FspmConfig.AttemptFastBootCold = 0x1; |
| 134 | |
| 135 | /* Set Adv MemTest Option to 0. */ |
| 136 | mupd->FspmConfig.AdvMemTestOptions = 0x0; |
| 137 | /* Set MRC Promote Warnings to disable. */ |
| 138 | /* Determines if MRC warnings are promoted to system level. */ |
| 139 | mupd->FspmConfig.promoteMrcWarnings = 0x0; |
| 140 | /* Set Promote Warnings to disable. */ |
| 141 | /* Determines if warnings are promoted to system level. */ |
| 142 | mupd->FspmConfig.promoteWarnings = 0x0; |
| 143 | |
| 144 | /* Reduce FSP debug message to Minimum */ |
| 145 | mupd->FspmConfig.serialDebugMsgLvl = 0x1; |
| 146 | |
| 147 | /* Disable FSP memory train results */ |
| 148 | mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; |
| 149 | |
| 150 | mainboard_config_iio(mupd); |
| 151 | } |