| Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef AMD_COMMON_ACP_H |
| 4 | #define AMD_COMMON_ACP_H |
| 5 | |
| 6 | struct acp_config { |
| 7 | enum { |
| 8 | I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ |
| 9 | I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ |
| 10 | I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ |
| 11 | I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ |
| 12 | I2S_PINS_I2S_TDM = 4, |
| 13 | I2S_PINS_UNCONF = 7, /* All pads will be input mode */ |
| 14 | } acp_pin_cfg; |
| 15 | |
| 16 | /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ |
| 17 | u8 acp_i2s_wake_enable; |
| 18 | /* Enable ACP PME (0 = disable, 1 = enable) */ |
| 19 | u8 acp_pme_enable; |
| 20 | |
| 21 | /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ |
| 22 | bool acp_i2s_use_external_48mhz_osc; |
| 23 | }; |
| 24 | |
| 25 | #endif /* AMD_COMMON_ACP_H */ |