Matt DeVillier | 61ba3ac | 2020-03-30 02:11:24 -0500 | [diff] [blame] | 1 | chip northbridge/intel/haswell |
| 2 | |
Angel Pons | d049579 | 2020-09-02 19:01:24 +0200 | [diff] [blame] | 3 | # Set panel power delays |
Michael Niewöhner | 44fa0d4 | 2020-12-28 15:00:39 +0100 | [diff] [blame^] | 4 | register "gpu_panel_power_cycle_delay_ms" = "400" |
| 5 | register "gpu_panel_power_up_delay_ms" = "40" |
| 6 | register "gpu_panel_power_down_delay_ms" = "15" |
| 7 | register "gpu_panel_power_backlight_on_delay_ms" = "210" |
| 8 | register "gpu_panel_power_backlight_off_delay_ms" = "210" |
Matt DeVillier | 61ba3ac | 2020-03-30 02:11:24 -0500 | [diff] [blame] | 9 | |
| 10 | device domain 0 on |
| 11 | |
| 12 | chip southbridge/intel/lynxpoint |
| 13 | |
| 14 | register "sata_devslp_disable" = "0x1" |
| 15 | |
| 16 | # DTLE DATA / EDGE values |
| 17 | register "sata_port0_gen3_dtle" = "0x5" |
| 18 | register "sata_port1_gen3_dtle" = "0x5" |
| 19 | |
| 20 | # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP |
| 21 | register "icc_clock_disable" = "0x013c0000" |
| 22 | |
| 23 | device pci 1f.3 on # SMBus |
| 24 | chip drivers/i2c/rtd2132 |
| 25 | # Panel Power Timings (1 ms units) |
| 26 | # Note: the panel Tx timings are very |
| 27 | # different from the LVDS bridge |
| 28 | # Tx timing settings. Below is a mapping |
| 29 | # for RTD2132 -> Panel timings. |
| 30 | # T1 = T2 |
| 31 | # T2 = T8 + T10 + T12 |
| 32 | # T3 = T14 |
| 33 | # T4 = T15 |
| 34 | # T5 = T9 + T11 + T13 |
| 35 | # T6 = T3 |
| 36 | # T7 = T4 |
| 37 | register "t1" = "0x14" |
| 38 | register "t2" = "0xdc" |
| 39 | register "t3" = "0x0e" |
| 40 | register "t4" = "0x02" |
| 41 | register "t5" = "0xdc" |
| 42 | register "t6" = "0x14" |
| 43 | register "t7" = "0x208" |
| 44 | # LVDS Swap settings are normal. |
| 45 | register "lvds_swap" = "0" |
| 46 | # Enable Spread Sprectrum at 0.5% |
| 47 | register "sscg_percent" = "0x05" |
| 48 | device i2c 35 on end # (8bit address: 0x6A) |
| 49 | end # rtd2132 |
| 50 | end # SMBus |
| 51 | end |
| 52 | end |
| 53 | end |