| Matt DeVillier | ae01122 | 2020-03-30 13:21:45 -0500 | [diff] [blame] | 1 | chip soc/intel/broadwell |
| 2 | |
| Angel Pons | f8d4745 | 2020-09-02 18:54:03 +0200 | [diff] [blame] | 3 | # Set panel power delays |
| Michael Niewöhner | 44fa0d4 | 2020-12-28 15:00:39 +0100 | [diff] [blame^] | 4 | register "gpu_panel_power_cycle_delay_ms" = "400" |
| 5 | register "gpu_panel_power_up_delay_ms" = "40" |
| 6 | register "gpu_panel_power_down_delay_ms" = "15" |
| 7 | register "gpu_panel_power_backlight_on_delay_ms" = "7" |
| 8 | register "gpu_panel_power_backlight_off_delay_ms" = "210" |
| Matt DeVillier | ae01122 | 2020-03-30 13:21:45 -0500 | [diff] [blame] | 9 | |
| Angel Pons | 99af210 | 2020-10-23 20:39:17 +0200 | [diff] [blame] | 10 | device domain 0 on |
| Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 11 | chip soc/intel/broadwell/pch |
| Angel Pons | 99af210 | 2020-10-23 20:39:17 +0200 | [diff] [blame] | 12 | # DTLE DATA / EDGE values |
| 13 | register "sata_port0_gen3_dtle" = "0x5" |
| 14 | register "sata_port1_gen3_dtle" = "0x5" |
| Angel Pons | d79b87a | 2020-10-25 16:44:22 +0100 | [diff] [blame] | 15 | |
| 16 | device pci 1f.2 on end # SATA Controller |
| Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 17 | end |
| Angel Pons | 99af210 | 2020-10-23 20:39:17 +0200 | [diff] [blame] | 18 | end |
| Matt DeVillier | ae01122 | 2020-03-30 13:21:45 -0500 | [diff] [blame] | 19 | end |