Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPMUPD_H__ |
| 34 | #define __FSPMUPD_H__ |
| 35 | |
| 36 | #include <FspUpd.h> |
| 37 | |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 38 | #pragma pack(push, 1) |
| 39 | |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 40 | |
| 41 | /** Fsp M Configuration |
| 42 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 43 | typedef struct { |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 44 | |
| 45 | /** Offset 0x0040 - RmuBaseAddress |
| 46 | RMU microcode binary base address in SPI flash' |
| 47 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 48 | UINT32 RmuBaseAddress; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 49 | |
| 50 | /** Offset 0x0044 - RmuLength |
| 51 | RMU microcode binary length in bytes |
| 52 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 53 | UINT32 RmuLength; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 54 | |
| 55 | /** Offset 0x0048 - SerialPortBaseAddress |
| 56 | Debug serial port base address set by BIOS. Zero disables debug serial output. |
| 57 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 58 | UINT32 Reserved_48; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 59 | |
| 60 | /** Offset 0x004C - tRAS |
| 61 | ACT to PRE command period in picoseconds. |
| 62 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 63 | UINT32 tRAS; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 64 | |
| 65 | /** Offset 0x0050 - tWTR |
| 66 | Delay from start of internal write transaction to internal read command in picoseconds. |
| 67 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 68 | UINT32 tWTR; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 69 | |
| 70 | /** Offset 0x0054 - tRRD |
| 71 | ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. |
| 72 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 73 | UINT32 tRRD; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 74 | |
| 75 | /** Offset 0x0058 - tFAW |
| 76 | Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. |
| 77 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 78 | UINT32 tFAW; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 79 | |
| 80 | /** Offset 0x005C - Flags |
| 81 | Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN |
| 82 | BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" |
| 83 | topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices |
| 84 | on writes. |
| 85 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 86 | UINT32 Flags; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 87 | |
| 88 | /** Offset 0x0060 - DramWidth |
| 89 | 0=x8, 1=x16, others=RESERVED. |
| 90 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 91 | UINT8 DramWidth; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 92 | |
| 93 | /** Offset 0x0061 - DramSpeed |
| 94 | 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. |
| 95 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 96 | UINT8 DramSpeed; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 97 | |
| 98 | /** Offset 0x0062 - DramType |
| 99 | 0=DDR3, 1=DDR3L, others=RESERVED. |
| 100 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 101 | UINT8 DramType; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 102 | |
| 103 | /** Offset 0x0063 - RankMask |
| 104 | bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. |
| 105 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 106 | UINT8 RankMask; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 107 | |
| 108 | /** Offset 0x0064 - ChanMask |
| 109 | bit[0] CHAN0_EN, others=RESERVED. |
| 110 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 111 | UINT8 ChanMask; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 112 | |
| 113 | /** Offset 0x0065 - ChanWidth |
| 114 | 1=x16, others=RESERVED. |
| 115 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 116 | UINT8 ChanWidth; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 117 | |
| 118 | /** Offset 0x0066 - AddrMode |
| 119 | 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. |
| 120 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 121 | UINT8 AddrMode; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 122 | |
| 123 | /** Offset 0x0067 - SrInt |
| 124 | 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. |
| 125 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 126 | UINT8 SrInt; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 127 | |
| 128 | /** Offset 0x0068 - SrTemp |
| 129 | 0=normal, 1=extended, others=RESERVED. |
| 130 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 131 | UINT8 SrTemp; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 132 | |
| 133 | /** Offset 0x0069 - DramRonVal |
| 134 | 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. |
| 135 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 136 | UINT8 DramRonVal; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 137 | |
| 138 | /** Offset 0x006A - DramRttNomVal |
| 139 | 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. |
| 140 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 141 | UINT8 DramRttNomVal; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 142 | |
| 143 | /** Offset 0x006B - DramRttWrVal |
| 144 | 0=off others=RESERVED. |
| 145 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 146 | UINT8 DramRttWrVal; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 147 | |
| 148 | /** Offset 0x006C - SocRdOdtVal |
| 149 | 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. |
| 150 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 151 | UINT8 SocRdOdtVal; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 152 | |
| 153 | /** Offset 0x006D - SocWrRonVal |
| 154 | 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. |
| 155 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 156 | UINT8 SocWrRonVal; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 157 | |
| 158 | /** Offset 0x006E - SocWrSlewRate |
| 159 | 0=2.5V/ns, 1=4V/ns, others=RESERVED. |
| 160 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 161 | UINT8 SocWrSlewRate; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 162 | |
| 163 | /** Offset 0x006F - DramDensity |
| 164 | 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. |
| 165 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 166 | UINT8 DramDensity; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 167 | |
| 168 | /** Offset 0x0070 - tCL |
| 169 | DRAM CAS Latency in clocks |
| 170 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 171 | UINT8 tCL; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 172 | |
| 173 | /** Offset 0x0071 - EccScrubInterval |
| 174 | ECC scrub interval in miliseconds 1..255 (0 works as feature disable |
| 175 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 176 | UINT8 EccScrubInterval; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 177 | |
| 178 | /** Offset 0x0072 - EccScrubBlkSize |
| 179 | Number of 32B blocks read for ECC scrub 2..16 |
| 180 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 181 | UINT8 EccScrubBlkSize; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 182 | |
| 183 | /** Offset 0x0073 - SmmTsegSize |
| 184 | Size of the SMM region in 1 MiB chunks |
| 185 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 186 | UINT8 SmmTsegSize; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 187 | |
| 188 | /** Offset 0x0074 - FspReservedMemoryLength |
| 189 | FSP reserved memory length in bytes |
| 190 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 191 | UINT32 FspReservedMemoryLength; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 192 | |
| 193 | /** Offset 0x0078 - MrcDataPtr |
| 194 | Pointer to saved MRC data |
| 195 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 196 | UINT32 MrcDataPtr; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 197 | |
| 198 | /** Offset 0x007C - MrcDataLength |
| 199 | Length of saved MRC data |
| 200 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 201 | UINT32 MrcDataLength; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 202 | |
| 203 | /** Offset 0x0080 |
| 204 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 205 | UINT32 SerialPortPollForChar; |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame] | 206 | |
| 207 | /** Offset 0x0084 |
| 208 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 209 | UINT32 SerialPortReadChar; |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame] | 210 | |
| 211 | /** Offset 0x0088 |
| 212 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 213 | UINT32 SerialPortWriteChar; |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame] | 214 | |
| 215 | /** Offset 0x008C |
| 216 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 217 | UINT16 UpdTerminator; |
| 218 | } FSP_M_CONFIG; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 219 | |
| 220 | /** Fsp M UPD Configuration |
| 221 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 222 | typedef struct { |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 223 | |
| 224 | /** Offset 0x0000 |
| 225 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 226 | FSP_UPD_HEADER FspUpdHeader; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 227 | |
| 228 | /** Offset 0x0020 |
| 229 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 230 | FSPM_ARCH_UPD FspmArchUpd; |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 231 | |
| 232 | /** Offset 0x0040 |
| 233 | **/ |
Lee Leahy | e165423 | 2016-09-28 14:10:06 -0700 | [diff] [blame] | 234 | FSP_M_CONFIG FspmConfig; |
| 235 | } FSPM_UPD; |
| 236 | |
| 237 | #pragma pack(pop) |
Lee Leahy | 38e0cc0 | 2016-07-25 07:00:50 -0700 | [diff] [blame] | 238 | |
| 239 | #endif |