Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 18 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 20 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 21 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 22 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 23 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 24 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 25 | #include "ec/compal/ene932/ec.h" |
| 26 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 27 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 28 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 29 | /* |
| 30 | * GFX INTA -> PIRQA (MSI) |
| 31 | * D28IP_P2IP WLAN INTA -> PIRQB |
| 32 | * D28IP_P3IP ETH0 INTC -> PIRQD |
| 33 | * D29IP_E1P EHCI1 INTA -> PIRQE |
| 34 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 35 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 36 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 37 | * D31IP_TTIP THRT INTC -> PIRQH |
| 38 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 39 | * |
| 40 | * Trackpad DVT PIRQA (16) |
| 41 | * Trackpad DVT PIRQE (20) |
| 42 | */ |
| 43 | |
| 44 | /* Device interrupt pin register (board specific) */ |
| 45 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 46 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 47 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 48 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 49 | RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | |
| 50 | (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | |
| 51 | (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | |
| 52 | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); |
| 53 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 54 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 55 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 56 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 57 | |
| 58 | /* Device interrupt route registers */ |
| 59 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 60 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 61 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 62 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 63 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 64 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 65 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 66 | } |
| 67 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 68 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 69 | { |
| 70 | struct pei_data pei_data_template = { |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 71 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 72 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 73 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 74 | .epbar = DEFAULT_EPBAR, |
| 75 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 76 | .smbusbar = SMBUS_IO_BASE, |
| 77 | .wdbbar = 0x4000000, |
| 78 | .wdbsize = 0x1000, |
| 79 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 80 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 81 | .pmbase = DEFAULT_PMBASE, |
| 82 | .gpiobase = DEFAULT_GPIOBASE, |
| 83 | .thermalbase = 0xfed08000, |
| 84 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 85 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 86 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 87 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 88 | .ec_present = 1, |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 89 | // 0 = leave channel enabled |
| 90 | // 1 = disable dimm 0 on channel |
| 91 | // 2 = disable dimm 1 on channel |
| 92 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 93 | .dimm_channel0_disabled = 2, |
| 94 | .dimm_channel1_disabled = 2, |
| 95 | .max_ddr3_freq = 1600, |
| 96 | .usb_port_config = { |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 97 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 98 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 99 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 100 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 101 | { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ |
| 102 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 103 | { 0, 3, 0x0000 }, /* P5: Empty */ |
| 104 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 105 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 106 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 107 | { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ |
| 108 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 109 | { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ |
| 110 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 111 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 112 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 113 | }, |
| 114 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 115 | *pei_data = pei_data_template; |
| 116 | } |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 117 | |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 118 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 119 | /* enabled power usb oc pin */ |
| 120 | { 0, 0, -1 }, /* P0: Empty */ |
| 121 | { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ |
| 122 | { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ |
| 123 | { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ |
| 124 | { 0, 0, -1 }, /* P4: Empty */ |
| 125 | { 0, 0, -1 }, /* P5: Empty */ |
| 126 | { 0, 0, -1 }, /* P6: Empty */ |
| 127 | { 0, 0, -1 }, /* P7: Empty */ |
| 128 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 129 | { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ |
| 130 | { 0, 0, -1 }, /* P9: Empty */ |
| 131 | { 1, 0, -1 }, /* P10: Camera (no OC) */ |
| 132 | { 0, 0, -1 }, /* P11: Empty */ |
| 133 | { 0, 0, -1 }, /* P12: Empty */ |
| 134 | { 0, 0, -1 }, /* P13: Empty */ |
| 135 | }; |
| 136 | |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 137 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 138 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 139 | read_spd(&spd[0], 0x50, id_only); |
| 140 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 141 | } |
| 142 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 143 | int mainboard_should_reset_usb(int s3resume) |
| 144 | { |
| 145 | return !s3resume; |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 146 | } |