Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <types.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 18 | #include <arch/io.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <cpu/x86/cache.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 21 | #include <device/pci_def.h> |
| 22 | #include <cpu/x86/smm.h> |
Duncan Laurie | 0920915 | 2012-06-23 17:25:29 -0700 | [diff] [blame] | 23 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 24 | #include <halt.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 25 | #include "pch.h" |
| 26 | |
| 27 | #include "nvs.h" |
| 28 | |
Duncan Laurie | 51cb26d | 2012-06-23 15:22:43 -0700 | [diff] [blame] | 29 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Vladimir Serbinenko | 4141b47 | 2015-05-16 13:48:10 +0200 | [diff] [blame] | 30 | #include <southbridge/intel/bd82x6x/me.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 31 | #include <southbridge/intel/common/gpio.h> |
Vladimir Serbinenko | 4141b47 | 2015-05-16 13:48:10 +0200 | [diff] [blame] | 32 | #include <cpu/intel/model_206ax/model_206ax.h> |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 33 | #include <southbridge/intel/common/pmutil.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 34 | #include <southbridge/intel/common/finalize.h> |
Duncan Laurie | 51cb26d | 2012-06-23 15:22:43 -0700 | [diff] [blame] | 35 | |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 36 | static global_nvs_t *gnvs; |
Duncan Laurie | 7f3d442 | 2012-10-03 19:01:57 -0700 | [diff] [blame] | 37 | global_nvs_t *smm_get_gnvs(void) |
| 38 | { |
| 39 | return gnvs; |
| 40 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 42 | int southbridge_io_trap_handler(int smif) |
| 43 | { |
| 44 | switch (smif) { |
| 45 | case 0x32: |
| 46 | printk(BIOS_DEBUG, "OS Init\n"); |
| 47 | /* gnvs->smif: |
| 48 | * On success, the IO Trap Handler returns 0 |
| 49 | * On failure, the IO Trap Handler returns a value != 0 |
| 50 | */ |
| 51 | gnvs->smif = 0; |
| 52 | return 1; /* IO trap handled */ |
| 53 | } |
| 54 | |
| 55 | /* Not handled */ |
| 56 | return 0; |
| 57 | } |
| 58 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 59 | static void southbridge_gate_memory_reset_real(int offset, |
| 60 | u16 use, u16 io, u16 lvl) |
| 61 | { |
| 62 | u32 reg32; |
| 63 | |
| 64 | /* Make sure it is set as GPIO */ |
| 65 | reg32 = inl(use); |
| 66 | if (!(reg32 & (1 << offset))) { |
| 67 | reg32 |= (1 << offset); |
| 68 | outl(reg32, use); |
| 69 | } |
| 70 | |
| 71 | /* Make sure it is set as output */ |
| 72 | reg32 = inl(io); |
| 73 | if (reg32 & (1 << offset)) { |
| 74 | reg32 &= ~(1 << offset); |
| 75 | outl(reg32, io); |
| 76 | } |
| 77 | |
| 78 | /* Drive the output low */ |
| 79 | reg32 = inl(lvl); |
| 80 | reg32 &= ~(1 << offset); |
| 81 | outl(reg32, lvl); |
| 82 | } |
| 83 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 84 | /* |
| 85 | * Drive GPIO 60 low to gate memory reset in S3. |
| 86 | * |
| 87 | * Intel reference designs all use GPIO 60 but it is |
| 88 | * not a requirement and boards could use a different pin. |
| 89 | */ |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 90 | void southbridge_gate_memory_reset(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 91 | { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 92 | u16 gpiobase; |
| 93 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 94 | gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 95 | if (!gpiobase) |
| 96 | return; |
| 97 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 98 | if (CONFIG_DRAM_RESET_GATE_GPIO >= 32) |
| 99 | southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32, |
| 100 | gpiobase + GPIO_USE_SEL2, |
| 101 | gpiobase + GP_IO_SEL2, |
| 102 | gpiobase + GP_LVL2); |
| 103 | else |
| 104 | southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO, |
| 105 | gpiobase + GPIO_USE_SEL, |
| 106 | gpiobase + GP_IO_SEL, |
| 107 | gpiobase + GP_LVL); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 108 | } |
| 109 | |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 110 | static void xhci_sleep(u8 slp_typ) |
| 111 | { |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 112 | u32 reg32, xhci_bar; |
| 113 | u16 reg16; |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 114 | |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 115 | switch (slp_typ) { |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 116 | case ACPI_S3: |
| 117 | case ACPI_S4: |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 118 | reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 119 | reg16 &= ~0x03UL; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 120 | pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 121 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 122 | reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 123 | reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 124 | pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 125 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 126 | xhci_bar = pci_read_config32(PCH_XHCI_DEV, |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 127 | PCI_BASE_ADDRESS_0) & ~0xFUL; |
| 128 | |
| 129 | if ((xhci_bar + 0x4C0) & 1) |
| 130 | pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); |
| 131 | if ((xhci_bar + 0x4D0) & 1) |
| 132 | pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); |
| 133 | if ((xhci_bar + 0x4E0) & 1) |
| 134 | pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); |
| 135 | if ((xhci_bar + 0x4F0) & 1) |
| 136 | pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); |
| 137 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 138 | reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 139 | reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 140 | pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 141 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 142 | reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 143 | reg16 |= 0x03; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 144 | pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 145 | break; |
| 146 | |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 147 | case ACPI_S5: |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 148 | reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 149 | reg16 |= ((1 << 8) | 0x03); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 150 | pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); |
Marc Jones | 058d70f | 2013-02-11 14:39:28 -0700 | [diff] [blame] | 151 | break; |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 152 | } |
| 153 | } |
| 154 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 155 | void southbridge_smi_monitor(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 156 | { |
| 157 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 158 | u32 trap_sts, trap_cycle; |
| 159 | u32 data, mask = 0; |
| 160 | int i; |
| 161 | |
| 162 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 163 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 164 | |
| 165 | trap_cycle = RCBA32(0x1e10); |
| 166 | for (i=16; i<20; i++) { |
| 167 | if (trap_cycle & (1 << i)) |
| 168 | mask |= (0xff << ((i - 16) << 2)); |
| 169 | } |
| 170 | |
| 171 | |
| 172 | /* IOTRAP(3) SMI function call */ |
| 173 | if (IOTRAP(3)) { |
| 174 | if (gnvs && gnvs->smif) |
| 175 | io_trap_handler(gnvs->smif); // call function smif |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | /* IOTRAP(2) currently unused |
| 180 | * IOTRAP(1) currently unused */ |
| 181 | |
| 182 | /* IOTRAP(0) SMIC */ |
| 183 | if (IOTRAP(0)) { |
| 184 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 185 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 186 | data = RCBA32(0x1e18); |
| 187 | data &= mask; |
| 188 | // if (smi1) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 189 | // southbridge_smi_command(data); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 190 | // return; |
| 191 | } |
| 192 | // Fall through to debug |
| 193 | } |
| 194 | |
| 195 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); |
Elyes HAOUAS | 70d79a4 | 2016-08-21 18:36:06 +0200 | [diff] [blame] | 196 | for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 197 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 198 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 199 | printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 200 | |
| 201 | if (!(trap_cycle & (1 << 24))) { |
| 202 | /* Write Cycle */ |
| 203 | data = RCBA32(0x1e18); |
| 204 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 205 | } |
| 206 | #undef IOTRAP |
| 207 | } |
| 208 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 209 | void southbridge_smm_xhci_sleep(u8 slp_type) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 210 | { |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 211 | if (smm_get_gnvs()->xhci) |
| 212 | xhci_sleep(slp_type); |
| 213 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 214 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 215 | void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) |
| 216 | { |
| 217 | em64t101_smm_state_save_area_t *state = |
| 218 | smi_apmc_find_state_save(apm_cnt); |
| 219 | if (state) { |
| 220 | /* EBX in the state save contains the GNVS pointer */ |
| 221 | gnvs = (global_nvs_t *)((u32)state->rbx); |
| 222 | *smm_done = 1; |
| 223 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 224 | } |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 225 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 226 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 227 | void southbridge_finalize_all(void) |
| 228 | { |
| 229 | intel_me_finalize_smm(); |
| 230 | intel_pch_finalize_smm(); |
| 231 | intel_sandybridge_finalize_smm(); |
| 232 | intel_model_206ax_finalize_smm(); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 233 | } |