Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 5 | * Copyright (C) 2017-2018 Intel Corporation. |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 17 | #include <console/console.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 18 | #include <device/device.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 19 | #include <intelblocks/fast_spi.h> |
Furquan Shaikh | 1876f3a | 2017-12-07 18:39:34 -0800 | [diff] [blame] | 20 | #include <intelblocks/gspi.h> |
Caveh Jalali | 1428f01 | 2018-01-23 22:15:24 -0800 | [diff] [blame] | 21 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 22 | #include <intelblocks/p2sb.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 23 | #include <intelblocks/pcr.h> |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 24 | #include <intelblocks/pmclib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 25 | #include <intelblocks/rtc.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 26 | #include <intelblocks/smbus.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 27 | #include <intelblocks/tco.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 28 | #include <soc/bootblock.h> |
| 29 | #include <soc/iomap.h> |
| 30 | #include <soc/lpc.h> |
| 31 | #include <soc/p2sb.h> |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 32 | #include <soc/pch.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
| 34 | #include <soc/pcr_ids.h> |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 35 | #include <soc/pm.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 36 | #include <soc/smbus.h> |
| 37 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 38 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 |
| 39 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 |
| 40 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 41 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 42 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 43 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 44 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 45 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 46 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 47 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 48 | |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 49 | #define PCR_DMI_DMICTL 0x2234 |
| 50 | #define PCR_DMI_DMICTL_SRLOCK (1 << 31) |
| 51 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 52 | #define PCR_DMI_ACPIBA 0x27B4 |
| 53 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 54 | #define PCR_DMI_PMBASEA 0x27AC |
| 55 | #define PCR_DMI_PMBASEC 0x27B0 |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 56 | |
| 57 | #define PCR_DMI_LPCIOD 0x2770 |
| 58 | #define PCR_DMI_LPCIOE 0x2774 |
| 59 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 60 | static uint32_t get_pmc_reg_base(void) |
| 61 | { |
| 62 | uint8_t pch_series; |
| 63 | |
| 64 | pch_series = get_pch_series(); |
| 65 | |
| 66 | if (pch_series == PCH_H) |
| 67 | return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; |
| 68 | else if (pch_series == PCH_LP) |
| 69 | return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; |
| 70 | else |
| 71 | return 0; |
| 72 | } |
| 73 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 74 | static void soc_config_pwrmbase(void) |
| 75 | { |
| 76 | uint32_t reg32; |
| 77 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 78 | /* |
| 79 | * Assign Resources to PWRMBASE |
| 80 | * Clear BIT 1-2 Command Register |
| 81 | */ |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 82 | reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); |
| 83 | reg32 &= ~(PCI_COMMAND_MEMORY); |
| 84 | pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); |
| 85 | |
| 86 | /* Program PWRM Base */ |
| 87 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 88 | |
| 89 | /* Enable Bus Master and MMIO Space */ |
| 90 | reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); |
| 91 | reg32 |= PCI_COMMAND_MEMORY; |
| 92 | pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); |
| 93 | |
| 94 | /* Enable PWRM in PMC */ |
| 95 | reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); |
| 96 | write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); |
| 97 | } |
| 98 | |
| 99 | void bootblock_pch_early_init(void) |
| 100 | { |
| 101 | fast_spi_early_init(SPI_BASE_ADDRESS); |
Furquan Shaikh | 1876f3a | 2017-12-07 18:39:34 -0800 | [diff] [blame] | 102 | gspi_early_bar_init(); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 103 | p2sb_enable_bar(); |
| 104 | p2sb_configure_hpet(); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 105 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 106 | /* |
| 107 | * Enabling PWRM Base for accessing |
| 108 | * Global Reset Cause Register. |
| 109 | */ |
| 110 | soc_config_pwrmbase(); |
| 111 | } |
| 112 | |
| 113 | |
| 114 | static void soc_config_acpibase(void) |
| 115 | { |
| 116 | uint32_t pmc_reg_value; |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 117 | uint32_t pmc_base_reg; |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 118 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 119 | pmc_base_reg = get_pmc_reg_base(); |
| 120 | if (!pmc_base_reg) |
| 121 | die("Invalid PMC base address\n"); |
| 122 | |
| 123 | pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + |
| 124 | PCR_PSFX_TO_SHDW_BAR4); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 125 | |
| 126 | if (pmc_reg_value != 0xFFFFFFFF) |
| 127 | { |
| 128 | /* Disable Io Space before changing the address */ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 129 | pcr_rmw32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 130 | PCR_PSFX_T0_SHDW_PCIEN, |
| 131 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 132 | /* Program ABASE in PSF3 PMC space BAR4*/ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 133 | pcr_write32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 134 | PCR_PSFX_TO_SHDW_BAR4, |
| 135 | ACPI_BASE_ADDRESS); |
| 136 | /* Enable IO Space */ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 137 | pcr_rmw32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 138 | PCR_PSFX_T0_SHDW_PCIEN, |
| 139 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 140 | } |
| 141 | } |
| 142 | |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 143 | static int pch_check_decode_enable(void) |
| 144 | { |
| 145 | uint32_t dmi_control; |
| 146 | |
| 147 | /* |
| 148 | * This cycle decoding is only allowed to set when |
| 149 | * DMICTL.SRLOCK is 0. |
| 150 | */ |
| 151 | dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); |
| 152 | if (dmi_control & PCR_DMI_DMICTL_SRLOCK) |
| 153 | return -1; |
| 154 | return 0; |
| 155 | } |
| 156 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 157 | void pch_early_iorange_init(void) |
| 158 | { |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 159 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 160 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 161 | |
| 162 | /* IO Decode Range */ |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 163 | if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) |
| 164 | lpc_io_setup_comm_a_b(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 165 | |
| 166 | /* IO Decode Enable */ |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 167 | if (pch_check_decode_enable() == 0) { |
| 168 | io_enables = lpc_enable_fixed_io_ranges(io_enables); |
| 169 | /* |
| 170 | * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same |
| 171 | * value program in LPC PCI offset 82h. |
| 172 | */ |
| 173 | pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); |
| 174 | } |
Caveh Jalali | 1428f01 | 2018-01-23 22:15:24 -0800 | [diff] [blame] | 175 | |
| 176 | /* Program generic IO Decode Range */ |
| 177 | pch_enable_lpc(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | void pch_early_init(void) |
| 181 | { |
| 182 | /* |
| 183 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 184 | * GPE0_STS, GPE0_EN registers. |
| 185 | */ |
| 186 | soc_config_acpibase(); |
| 187 | |
| 188 | /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 189 | tco_configure(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 190 | |
| 191 | /* Program SMBUS_BASE_ADDRESS and Enable it */ |
| 192 | smbus_common_init(); |
| 193 | |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 194 | /* Set up GPE configuration */ |
| 195 | pmc_gpe_init(); |
| 196 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 197 | enable_rtc_upper_bank(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 198 | } |