Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <cpu/x86/lapic.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 18 | #include <northbridge/amd/amdfam10/raminit.h> |
| 19 | #include <northbridge/amd/amdfam10/amdfam10.h> |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 20 | |
| 21 | /* mmconf is not ready */ |
| 22 | /* io_ext is not ready */ |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 23 | u32 cpu_init_detected(u8 nodeid) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 24 | { |
| 25 | u32 htic; |
Edward O'Callaghan | 3ec9c95 | 2014-10-26 10:36:02 +1100 | [diff] [blame] | 26 | pci_devfn_t dev; |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 27 | |
| 28 | dev = NODE_PCI(nodeid, 0); |
| 29 | htic = pci_io_read_config32(dev, HT_INIT_CONTROL); |
| 30 | |
| 31 | return !!(htic & HTIC_INIT_Detect); |
| 32 | } |
| 33 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 34 | u32 bios_reset_detected(void) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 35 | { |
| 36 | u32 htic; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 37 | htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 38 | |
| 39 | return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); |
| 40 | } |
| 41 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 42 | u32 cold_reset_detected(void) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 43 | { |
| 44 | u32 htic; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 45 | htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 46 | |
| 47 | return !(htic & HTIC_ColdR_Detect); |
| 48 | } |
| 49 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 50 | u32 other_reset_detected(void) // other warm reset not started by BIOS |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 51 | { |
| 52 | u32 htic; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 53 | htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 54 | |
| 55 | return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); |
| 56 | } |
| 57 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 58 | void distinguish_cpu_resets(u8 nodeid) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 59 | { |
| 60 | u32 htic; |
Edward O'Callaghan | 3ec9c95 | 2014-10-26 10:36:02 +1100 | [diff] [blame] | 61 | pci_devfn_t device; |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 62 | device = NODE_PCI(nodeid, 0); |
| 63 | htic = pci_io_read_config32(device, HT_INIT_CONTROL); |
| 64 | htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; |
| 65 | pci_io_write_config32(device, HT_INIT_CONTROL, htic); |
| 66 | } |
| 67 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 68 | u32 warm_reset_detect(u8 nodeid) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 69 | { |
| 70 | u32 htic; |
Edward O'Callaghan | 3ec9c95 | 2014-10-26 10:36:02 +1100 | [diff] [blame] | 71 | pci_devfn_t device; |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 72 | device = NODE_PCI(nodeid, 0); |
| 73 | htic = pci_io_read_config32(device, HT_INIT_CONTROL); |
| 74 | return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); |
| 75 | } |
| 76 | |
Vladimir Serbinenko | bf8722a | 2014-11-09 13:17:39 +0100 | [diff] [blame] | 77 | void set_bios_reset(void) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 78 | { |
| 79 | |
| 80 | u32 nodes; |
| 81 | u32 htic; |
Edward O'Callaghan | 3ec9c95 | 2014-10-26 10:36:02 +1100 | [diff] [blame] | 82 | pci_devfn_t dev; |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 83 | int i; |
| 84 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 85 | nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 86 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 87 | for (i = 0; i < nodes; i++) { |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 88 | dev = NODE_PCI(i,0); |
| 89 | htic = pci_read_config32(dev, HT_INIT_CONTROL); |
| 90 | htic &= ~HTIC_BIOSR_Detect; |
| 91 | pci_write_config32(dev, HT_INIT_CONTROL, htic); |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | |
| 96 | /* Look up a which bus a given node/link combination is on. |
| 97 | * return 0 when we can't find the answer. |
| 98 | */ |
| 99 | static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three bit |
| 100 | { |
| 101 | u32 reg; |
| 102 | u32 val; |
| 103 | |
| 104 | // put node and link in correct bit |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 105 | val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 106 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 107 | for (reg = 0xE0; reg < 0xF0; reg += 0x04) { |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 108 | u32 config_map; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 109 | config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 110 | if ((config_map & 3) != 3) { |
| 111 | continue; |
| 112 | } |
Elyes HAOUAS | 04f8fd9 | 2016-09-19 10:24:34 -0600 | [diff] [blame] | 113 | if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8)) |
| 114 | ) == val) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 115 | { |
| 116 | return (config_map >> 16) & 0xff; |
| 117 | } |
| 118 | } |
| 119 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 120 | return 0; |
| 121 | } |
| 122 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 123 | u32 get_sblk(void) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 124 | { |
| 125 | u32 reg; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 126 | /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ |
| 127 | reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 128 | return ((reg>>8) & 3); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 132 | u8 get_sbbusn(u8 sblk) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 133 | { |
| 134 | return node_link_to_bus(0, sblk); |
| 135 | } |