WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <device/pci_def.h> |
Kyösti Mälkki | 207880c | 2013-12-10 09:03:17 +0200 | [diff] [blame] | 19 | #include <arch/acpi.h> |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 20 | #include <arch/io.h> |
Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 21 | #include <commonlib/loglevel.h> |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 22 | |
| 23 | #include <northbridge/amd/agesa/state_machine.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 24 | #include <southbridge/amd/agesa/hudson/hudson.h> |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 25 | |
Edward O'Callaghan | 92da206 | 2014-05-13 23:52:30 +1000 | [diff] [blame] | 26 | #include <superio/winbond/common/winbond.h> |
| 27 | #include <superio/winbond/w83627uhg/w83627uhg.h> |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 28 | |
| 29 | #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) |
| 30 | |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 31 | void board_BeforeAgesa(struct sysinfo *cb) |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 32 | { |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 33 | volatile u32 *addr32; |
| 34 | u32 t32; |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 35 | |
Kyösti Mälkki | 88ff8b5 | 2014-11-21 17:40:37 +0200 | [diff] [blame] | 36 | /* Set LPC decode enables. */ |
| 37 | pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
| 38 | pci_write_config32(dev, 0x44, 0xff03ffd5); |
| 39 | |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 40 | hudson_lpc_port80(); |
| 41 | |
| 42 | /* Enable the AcpiMmio space */ |
| 43 | outb(0x24, 0xcd6); |
| 44 | outb(0x1, 0xcd7); |
| 45 | |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 46 | /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ |
| 47 | outb(0xea, 0xcd6); |
| 48 | outb(0x1, 0xcd7); |
| 49 | |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 50 | /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ |
| 51 | addr32 = (u32 *)0xfed80e28; |
| 52 | t32 = *addr32; |
| 53 | t32 &= 0xfff8ffff; |
| 54 | *addr32 = t32; |
| 55 | |
| 56 | /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ |
| 57 | addr32 = (u32 *)0xfed80e40; |
| 58 | t32 = *addr32; |
| 59 | t32 &= 0xffffbffb; |
| 60 | *addr32 = t32; |
| 61 | |
Kyösti Mälkki | 1dea4b1 | 2016-12-20 06:43:45 +0200 | [diff] [blame] | 62 | /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ |
| 63 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 64 | } |