Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/device.h> |
Elyes Haouas | cbbbb6c | 2022-10-22 22:15:27 +0200 | [diff] [blame] | 4 | #include <device/pci_def.h> |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 5 | #include <intelblocks/pcie_rp.h> |
| 6 | #include <soc/pci_devs.h> |
Elyes Haouas | cbbbb6c | 2022-10-22 22:15:27 +0200 | [diff] [blame] | 7 | #include <stdbool.h> |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 8 | |
Tim Wawrzynczak | 8d0e77b | 2021-12-08 10:40:02 -0700 | [diff] [blame] | 9 | #define CPU_CPIE_VW_IDX_BASE 24 |
| 10 | |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 11 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 12 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 13 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 14 | { 0 } |
| 15 | }; |
| 16 | |
Michael Niewöhner | 7a2bc06 | 2022-01-09 02:17:30 +0100 | [diff] [blame] | 17 | static const struct pcie_rp_group pch_h_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 18 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 19 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, |
| 20 | { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, |
Michael Niewöhner | 7a2bc06 | 2022-01-09 02:17:30 +0100 | [diff] [blame] | 21 | { 0 } |
| 22 | }; |
| 23 | |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 24 | static const struct pcie_rp_group cpu_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 25 | { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3, .lcap_port_base = 1 }, |
| 26 | { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1, .lcap_port_base = 1 }, |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 27 | { 0 } |
| 28 | }; |
| 29 | |
| 30 | static bool is_part_of_group(const struct device *dev, |
| 31 | const struct pcie_rp_group *groups) |
| 32 | { |
| 33 | if (dev->path.type != DEVICE_PATH_PCI) |
| 34 | return false; |
| 35 | |
| 36 | const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); |
| 37 | const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); |
| 38 | const struct pcie_rp_group *group; |
| 39 | unsigned int i; |
| 40 | unsigned int fn; |
| 41 | |
| 42 | for (group = groups; group->count; ++group) { |
| 43 | for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { |
| 44 | if (slot_to_find == group->slot && fn_to_find == fn) |
| 45 | return true; |
| 46 | } |
| 47 | } |
| 48 | |
| 49 | return false; |
| 50 | } |
| 51 | |
Michael Niewöhner | 7a2bc06 | 2022-01-09 02:17:30 +0100 | [diff] [blame] | 52 | const struct pcie_rp_group *soc_get_pch_rp_groups(void) |
| 53 | { |
| 54 | if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)) |
| 55 | return pch_h_rp_groups; |
| 56 | else |
| 57 | return pch_lp_rp_groups; |
| 58 | } |
| 59 | |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 60 | enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) |
| 61 | { |
Michael Niewöhner | 7a2bc06 | 2022-01-09 02:17:30 +0100 | [diff] [blame] | 62 | const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups(); |
| 63 | |
| 64 | if (is_part_of_group(dev, pch_rp_groups)) |
Tim Wawrzynczak | 1ac0dc1 | 2021-12-02 16:19:14 -0700 | [diff] [blame] | 65 | return PCIE_RP_PCH; |
| 66 | |
| 67 | if (is_part_of_group(dev, cpu_rp_groups)) |
| 68 | return PCIE_RP_CPU; |
| 69 | |
| 70 | return PCIE_RP_UNKNOWN; |
| 71 | } |
Tim Wawrzynczak | 8d0e77b | 2021-12-08 10:40:02 -0700 | [diff] [blame] | 72 | |
| 73 | int soc_get_cpu_rp_vw_idx(const struct device *dev) |
| 74 | { |
| 75 | if (dev->path.type != DEVICE_PATH_PCI) |
| 76 | return -1; |
| 77 | |
| 78 | switch (dev->path.pci.devfn) { |
| 79 | case SA_DEVFN_PEG1: |
| 80 | return CPU_CPIE_VW_IDX_BASE + 2; |
| 81 | case SA_DEVFN_PEG2: |
| 82 | return CPU_CPIE_VW_IDX_BASE + 1; |
| 83 | case SA_DEVFN_PEG3: |
| 84 | return CPU_CPIE_VW_IDX_BASE; |
| 85 | case SA_DEVFN_CPU_PCIE: |
| 86 | return CPU_CPIE_VW_IDX_BASE + 3; |
| 87 | default: |
| 88 | return -1; |
| 89 | } |
| 90 | } |