Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Dinesh Gehlot | 3e86681 | 2023-01-17 05:57:56 +0000 | [diff] [blame] | 3 | #include <gpio.h> |
Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 4 | #include <intelblocks/pcr.h> |
| 5 | #include <soc/pcr_ids.h> |
| 6 | #include <soc/pmc.h> |
| 7 | |
| 8 | /* |
| 9 | * This file is created based on Intel Tiger Lake Processor PCH Datasheet |
| 10 | * Document number: 619207 |
| 11 | * Chapter number: 27 |
| 12 | */ |
| 13 | |
| 14 | static const struct reset_mapping rst_map[] = { |
| 15 | { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, |
| 16 | { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, |
| 17 | { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, |
| 18 | }; |
| 19 | static const struct reset_mapping rst_map_com2[] = { |
| 20 | { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, |
| 21 | { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, |
| 22 | { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, |
| 23 | { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, |
| 24 | }; |
| 25 | |
| 26 | /* |
| 27 | * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad |
| 28 | * group, regardless of whether or not there is a physical pad for each |
| 29 | * exposed GPIO number. |
| 30 | * |
| 31 | * This results in the OS having a sparse GPIO map, and devices that need |
| 32 | * to export an ACPI GPIO must use the OS expected number. |
| 33 | * |
| 34 | * Not all pins are usable as GPIO and those groups do not have a pad base. |
| 35 | * |
| 36 | * This layout matches the Linux kernel pinctrl map for TGL-H at: |
| 37 | * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c |
| 38 | */ |
| 39 | static const struct pad_group tgl_community0_groups[] = { |
| 40 | INTEL_GPP_BASE(GPIO_COM0_START, GPP_SPI0_IO_2, GPP_ESPI_CLK_LOOPBK, 0), /* GPP_A */ |
| 41 | INTEL_GPP_BASE(GPIO_COM0_START, GPP_R0, GPP_R19, 32), /* GPP_R */ |
| 42 | INTEL_GPP_BASE(GPIO_COM0_START, GPP_B0, GPP_GSPI1_CLK_LOOPBK, 64), /* GPP_B */ |
| 43 | INTEL_GPP_BASE(GPIO_COM0_START, ESPI_USB_OCB_0, USB_CPU_OCB_3, 96), /* vGPIO_0 */ |
| 44 | }; |
| 45 | |
| 46 | static const struct pad_group tgl_community1_groups[] = { |
| 47 | INTEL_GPP_BASE(GPIO_COM1_START, GPP_D0, GPP_GSPI3_CLK_LOOPBK, 128), /* GPP_D */ |
| 48 | INTEL_GPP_BASE(GPIO_COM1_START, GPP_C0, GPP_C23, 160), /* GPP_C */ |
| 49 | INTEL_GPP_BASE(GPIO_COM1_START, GPP_S0, GPP_S7, 192), /* GPP_S */ |
| 50 | INTEL_GPP_BASE(GPIO_COM1_START, GPP_G0, GPP_GSPI2_CLK_LOOPBK, 224), /* GPP_G */ |
| 51 | INTEL_GPP_BASE(GPIO_COM1_START, CNV_BTEN, vI2S2_RXD, 256), /* vGPIO */ |
| 52 | }; |
| 53 | |
| 54 | /* This community is not visible to the OS */ |
| 55 | static const struct pad_group tgl_community2_groups[] = { |
| 56 | INTEL_GPP(GPIO_COM2_START, GPD0, GPD12), /* GPD */ |
| 57 | }; |
| 58 | |
| 59 | static const struct pad_group tgl_community3_groups[] = { |
| 60 | INTEL_GPP_BASE(GPIO_COM3_START, GPP_E0, GPP_E12, 288), /* GPP_E */ |
| 61 | INTEL_GPP_BASE(GPIO_COM3_START, GPP_F0, GPP_F23, 320), /* GPP_F */ |
| 62 | }; |
| 63 | |
| 64 | static const struct pad_group tgl_community4_groups[] = { |
| 65 | INTEL_GPP_BASE(GPIO_COM4_START, GPP_H0, GPP_H23, 352), /* GPP_H */ |
| 66 | INTEL_GPP_BASE(GPIO_COM4_START, GPP_J0, GPP_J9, 384), /* GPP_J */ |
| 67 | INTEL_GPP_BASE(GPIO_COM4_START, GPP_K0, GPP_MLK_RSTB, 416), /* GPP_K */ |
| 68 | }; |
| 69 | |
| 70 | static const struct pad_group tgl_community5_groups[] = { |
| 71 | INTEL_GPP_BASE(GPIO_COM5_START, GPP_I0, GPP_I14, 448), /* GPP_I */ |
| 72 | INTEL_GPP(GPIO_COM5_START, GPP_JTAG_TDO, GPP_JTAG_CPU_TRSTB), /* JTAG */ |
| 73 | }; |
| 74 | |
| 75 | static const struct pad_community tgl_communities[] = { |
| 76 | [COMM_0] = { /* GPP A, R, B, vGPIO_0 */ |
| 77 | .port = PID_GPIOCOM0, |
| 78 | .first_pad = GPIO_COM0_START, |
| 79 | .last_pad = GPIO_COM0_END, |
| 80 | .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, |
| 81 | .pad_cfg_base = PAD_CFG_BASE, |
| 82 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 83 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 84 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 85 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 86 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 87 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 88 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 89 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 90 | .name = "GPP_ARB", |
| 91 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 92 | .reset_map = rst_map, |
| 93 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 94 | .groups = tgl_community0_groups, |
| 95 | .num_groups = ARRAY_SIZE(tgl_community0_groups), |
| 96 | }, |
| 97 | [COMM_1] = { /* GPP D, C, S, G, vGPIO */ |
| 98 | .port = PID_GPIOCOM1, |
| 99 | .first_pad = GPIO_COM1_START, |
| 100 | .last_pad = GPIO_COM1_END, |
| 101 | .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, |
| 102 | .pad_cfg_base = PAD_CFG_BASE, |
| 103 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 104 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 105 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 106 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 107 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 108 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 109 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 110 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 111 | .name = "GPP_DCSG", |
| 112 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 113 | .reset_map = rst_map, |
| 114 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 115 | .groups = tgl_community1_groups, |
| 116 | .num_groups = ARRAY_SIZE(tgl_community1_groups), |
| 117 | }, |
| 118 | [COMM_2] = { /* GPD */ |
| 119 | .port = PID_GPIOCOM2, |
| 120 | .first_pad = GPIO_COM2_START, |
| 121 | .last_pad = GPIO_COM2_END, |
| 122 | .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, |
| 123 | .pad_cfg_base = PAD_CFG_BASE, |
| 124 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 125 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 126 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 127 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 128 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
| 129 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 130 | .name = "GPD", |
| 131 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 132 | .reset_map = rst_map_com2, |
| 133 | .num_reset_vals = ARRAY_SIZE(rst_map_com2), |
| 134 | .groups = tgl_community2_groups, |
| 135 | .num_groups = ARRAY_SIZE(tgl_community2_groups), |
| 136 | }, |
| 137 | [COMM_3] = { /* GPP E, F */ |
| 138 | .port = PID_GPIOCOM3, |
| 139 | .first_pad = GPIO_COM3_START, |
| 140 | .last_pad = GPIO_COM3_END, |
| 141 | .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, |
| 142 | .pad_cfg_base = PAD_CFG_BASE, |
| 143 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 144 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 145 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 146 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 147 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 148 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 149 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Jeremy Soller | 21d7c47 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 150 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 151 | .name = "GPP_EF", |
| 152 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 153 | .reset_map = rst_map, |
| 154 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 155 | .groups = tgl_community3_groups, |
| 156 | .num_groups = ARRAY_SIZE(tgl_community3_groups), |
| 157 | }, |
| 158 | [COMM_4] = { /* GPP H, J, K */ |
| 159 | .port = PID_GPIOCOM4, |
| 160 | .first_pad = GPIO_COM4_START, |
| 161 | .last_pad = GPIO_COM4_END, |
| 162 | .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, |
| 163 | .pad_cfg_base = PAD_CFG_BASE, |
| 164 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 165 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 166 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 167 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 168 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
| 169 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 170 | .name = "GPP_HJK", |
| 171 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 172 | .reset_map = rst_map, |
| 173 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 174 | .groups = tgl_community4_groups, |
| 175 | .num_groups = ARRAY_SIZE(tgl_community4_groups), |
| 176 | }, |
| 177 | [COMM_5] = { /* GPP I, JTAG */ |
| 178 | .port = PID_GPIOCOM5, |
| 179 | .first_pad = GPIO_COM5_START, |
| 180 | .last_pad = GPIO_COM5_END, |
| 181 | .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, |
| 182 | .pad_cfg_base = PAD_CFG_BASE, |
| 183 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 184 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 185 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
| 186 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 187 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
| 188 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 189 | .name = "GPP_I", |
| 190 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 191 | .reset_map = rst_map, |
| 192 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 193 | .groups = tgl_community5_groups, |
| 194 | .num_groups = ARRAY_SIZE(tgl_community5_groups), |
| 195 | }, |
| 196 | }; |
| 197 | |
| 198 | const struct pad_community *soc_gpio_get_community(size_t *num_communities) |
| 199 | { |
| 200 | *num_communities = ARRAY_SIZE(tgl_communities); |
| 201 | return tgl_communities; |
| 202 | } |
| 203 | |
| 204 | const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) |
| 205 | { |
| 206 | static const struct pmc_to_gpio_route routes[] = { |
| 207 | { PMC_GPD, GPD }, |
| 208 | { PMC_GPP_A, GPP_A }, |
| 209 | { PMC_GPP_B, GPP_B }, |
| 210 | { PMC_GPP_C, GPP_C }, |
| 211 | { PMC_GPP_D, GPP_D }, |
| 212 | { PMC_GPP_E, GPP_E }, |
| 213 | { PMC_GPP_F, GPP_F }, |
| 214 | { PMC_GPP_G, GPP_G }, |
| 215 | { PMC_GPP_H, GPP_H }, |
| 216 | { PMC_GPP_I, GPP_I }, |
| 217 | { PMC_GPP_J, GPP_J }, |
| 218 | { PMC_GPP_K, GPP_K }, |
| 219 | { PMC_GPP_R, GPP_R }, |
| 220 | { PMC_GPP_S, GPP_S }, |
| 221 | }; |
| 222 | *num = ARRAY_SIZE(routes); |
| 223 | return routes; |
| 224 | } |