Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
Dinesh Gehlot | a464af4 | 2023-01-17 05:23:16 +0000 | [diff] [blame] | 7 | #include <gpio.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 9 | #include <intelblocks/gspi.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 10 | #include <intelblocks/pcie_rp.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
| 12 | #include <soc/gpe.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 13 | #include <soc/pch.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/pmc.h> |
| 16 | #include <soc/serialio.h> |
| 17 | #include <soc/usb.h> |
Werner Zeh | 6ffbae3 | 2023-01-10 16:44:23 +0100 | [diff] [blame] | 18 | #include <types.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 19 | |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 20 | #define MAX_HD_AUDIO_SDI_LINKS 2 |
| 21 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 22 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 23 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 24 | #define MAX_PSE_TSN_PORTS 2 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 25 | |
Werner Zeh | bab5d50 | 2021-06-16 12:30:36 +0200 | [diff] [blame] | 26 | /* Define config parameters for In-Band ECC (IBECC). */ |
| 27 | #define MAX_IBECC_REGIONS 8 |
| 28 | |
| 29 | enum ibecc_mode { |
| 30 | IBECC_PER_REGION, |
| 31 | IBECC_NONE, |
| 32 | IBECC_ALL |
| 33 | }; |
| 34 | |
| 35 | struct ehl_ibecc_config { |
| 36 | bool enable; |
| 37 | bool parity_en; |
| 38 | enum ibecc_mode mode; |
| 39 | bool region_enable[MAX_IBECC_REGIONS]; |
| 40 | uint16_t region_base[MAX_IBECC_REGIONS]; |
| 41 | uint16_t region_mask[MAX_IBECC_REGIONS]; |
| 42 | }; |
| 43 | |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 44 | /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ |
| 45 | enum tsn_gbe_link_speed { |
| 46 | Tsn_2_5_Gbps, |
| 47 | Tsn_1_Gbps, |
| 48 | }; |
| 49 | |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 50 | /* TSN Phy Interface Type: 1: RGMII, 2: SGMII, 3:SGMII+ */ |
| 51 | enum tsn_phy_type { |
| 52 | RGMII = 1, |
| 53 | SGMII = 2, |
| 54 | SGMII_plus = 3, |
| 55 | }; |
| 56 | |
Mario Scheithauer | dccdace | 2022-04-27 11:24:05 +0200 | [diff] [blame] | 57 | /* TSN GBE PHY-to-MAC IRQ polarity: 0: falling edge, 1: rising edge */ |
| 58 | enum tsn_phy_irq_polarity { |
| 59 | FALLING_EDGE, |
| 60 | RISING_EDGE, |
| 61 | }; |
| 62 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 63 | /* |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 64 | * PSE native pins and ownership assignment:- |
| 65 | * 0: Disable/pins are not owned by PSE/host |
| 66 | * 1: Pins are muxed to PSE IP, the IO is owned by PSE |
| 67 | * 2: Pins are muxed to PSE IP, the IO is owned by host |
| 68 | */ |
| 69 | enum pse_device_ownership { |
| 70 | Device_Disabled, |
| 71 | PSE_Owned, |
| 72 | Host_Owned, |
| 73 | }; |
| 74 | |
| 75 | /* |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 76 | * Enable external V1P05 Rail in: BIT0:S0i1/S0i2, |
| 77 | * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 |
| 78 | * However, EHL does not support S0i1 and S0i2, |
| 79 | * hence removed the option. |
| 80 | */ |
| 81 | enum fivr_states { |
| 82 | FIVR_ENABLE_S0i3 = BIT(1), |
| 83 | FIVR_ENABLE_S3 = BIT(2), |
| 84 | FIVR_ENABLE_S4 = BIT(3), |
| 85 | FIVR_ENABLE_S5 = BIT(4), |
| 86 | FIVR_ENABLE_S3_S4_S5 = FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5, |
| 87 | FIVR_ENABLE_ALL_SX = FIVR_ENABLE_S0i3 | FIVR_ENABLE_S3_S4_S5, |
| 88 | }; |
| 89 | |
| 90 | /* |
| 91 | * Enable the following for external V1p05 rail |
| 92 | * BIT1: Normal active voltage supported |
| 93 | * BIT2: Minimum active voltage supported |
| 94 | * BIT3: Minimum retention voltage supported |
| 95 | */ |
| 96 | enum fivr_supported_voltage { |
| 97 | FIVR_VOLTAGE_NORMAL = BIT(1), |
| 98 | FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), |
| 99 | FIVR_VOLTAGE_MIN_RETENTION = BIT(3), |
| 100 | FIVR_ENABLE_ALL_VOLTAGE = FIVR_VOLTAGE_NORMAL | FIVR_VOLTAGE_MIN_ACTIVE | |
| 101 | FIVR_VOLTAGE_MIN_RETENTION, |
| 102 | }; |
| 103 | |
Werner Zeh | 921bb34 | 2022-12-22 11:05:17 +0100 | [diff] [blame] | 104 | /* SATA speed limit */ |
| 105 | enum sata_speed_limit { |
| 106 | SATA_DEFAULT = 0, |
| 107 | SATA_GEN1, |
| 108 | SATA_GEN2 |
| 109 | }; |
| 110 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 111 | struct soc_intel_elkhartlake_config { |
| 112 | |
| 113 | /* Common struct containing soc config data required by common code */ |
| 114 | struct soc_intel_common_config common_soc_config; |
| 115 | |
| 116 | /* Common struct containing power limits configuration information */ |
| 117 | struct soc_power_limits_config power_limits_config; |
| 118 | |
| 119 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 120 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 121 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 122 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 123 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 124 | |
| 125 | /* Generic IO decode ranges */ |
| 126 | uint32_t gen1_dec; |
| 127 | uint32_t gen2_dec; |
| 128 | uint32_t gen3_dec; |
| 129 | uint32_t gen4_dec; |
| 130 | |
| 131 | /* Enable S0iX support */ |
| 132 | int s0ix_enable; |
| 133 | /* Enable DPTF support */ |
| 134 | int dptf_enable; |
| 135 | |
| 136 | /* Deep SX enable for both AC and DC */ |
| 137 | int deep_s3_enable_ac; |
| 138 | int deep_s3_enable_dc; |
| 139 | int deep_s5_enable_ac; |
| 140 | int deep_s5_enable_dc; |
| 141 | |
| 142 | /* Deep Sx Configuration |
| 143 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 144 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 145 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 146 | uint32_t deep_sx_config; |
| 147 | |
| 148 | /* TCC activation offset */ |
| 149 | uint32_t tcc_offset; |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 150 | uint32_t tcc_offset_clamp; |
| 151 | |
| 152 | /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ |
| 153 | bool MemoryThermalThrottlingDisable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 154 | |
Werner Zeh | bab5d50 | 2021-06-16 12:30:36 +0200 | [diff] [blame] | 155 | /* In-Band ECC (IBECC) configuration */ |
| 156 | struct ehl_ibecc_config ibecc; |
| 157 | |
Lean Sheng Tan | 0cdcdc7 | 2021-06-08 23:41:15 -0700 | [diff] [blame] | 158 | /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ |
| 159 | bool FuSaEnable; |
| 160 | |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 161 | /* System Agent dynamic frequency support. |
| 162 | * When enabled memory will be trained at different frequencies. |
| 163 | * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 |
| 164 | * (high), 4:Enabled */ |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 165 | enum { |
| 166 | SaGv_Disabled, |
| 167 | SaGv_FixedPoint0, |
| 168 | SaGv_FixedPoint1, |
| 169 | SaGv_FixedPoint2, |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 170 | SaGv_Enabled, |
| 171 | } SaGv; |
| 172 | |
| 173 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 174 | uint8_t RMT; |
| 175 | |
| 176 | /* USB related */ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 177 | struct usb2_port_config usb2_ports[10]; |
| 178 | struct usb3_port_config usb3_ports[4]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 179 | /* Wake Enable Bitmap for USB2 ports */ |
| 180 | uint16_t usb2_wake_enable_bitmap; |
| 181 | /* Wake Enable Bitmap for USB3 ports */ |
| 182 | uint16_t usb3_wake_enable_bitmap; |
| 183 | |
| 184 | /* SATA related */ |
| 185 | uint8_t SataMode; |
| 186 | uint8_t SataSalpSupport; |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 187 | uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS]; |
| 188 | uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS]; |
Mario Scheithauer | 15e7499 | 2023-05-05 10:08:45 +0200 | [diff] [blame] | 189 | uint8_t SataPortsSSD[CONFIG_MAX_SATA_PORTS]; |
Werner Zeh | 921bb34 | 2022-12-22 11:05:17 +0100 | [diff] [blame] | 190 | enum sata_speed_limit SataSpeed; |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 191 | /* |
| 192 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 193 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 194 | */ |
| 195 | uint8_t SataPwrOptimizeDisable; |
| 196 | /* |
| 197 | * SATA Port Enable Dito Config. |
| 198 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 199 | */ |
| 200 | uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS]; |
| 201 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 202 | uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS]; |
| 203 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 204 | uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 205 | |
| 206 | /* Audio related */ |
| 207 | uint8_t PchHdaDspEnable; |
| 208 | uint8_t PchHdaAudioLinkHdaEnable; |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 209 | uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 210 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 211 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 212 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 213 | |
| 214 | /* PCIe Root Ports */ |
| 215 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 216 | uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; |
| 217 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 218 | /* PCIe output clocks type to PCIe devices. |
| 219 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 220 | * 0xFF: not used */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 221 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 222 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 223 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 224 | * clksrc. */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 225 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 226 | |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 227 | /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 228 | uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; |
| 229 | |
| 230 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management. |
| 231 | * Enable - Default (0) / Disable (1) */ |
| 232 | uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; |
| 233 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 234 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 235 | uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; |
| 236 | |
| 237 | /* PCIe LTR: Enable - Default (0) / Disable (1) */ |
| 238 | uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 239 | |
| 240 | /* PCIe RP L1 substate */ |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 241 | enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 242 | |
Mario Scheithauer | f5a4898 | 2023-05-10 14:25:24 +0200 | [diff] [blame] | 243 | /* PCIe root port maximum payload size, default is set to 128 bytes. */ |
| 244 | enum { |
| 245 | RpMaxPayload_128, |
| 246 | RpMaxPayload_256, |
| 247 | } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; |
| 248 | |
Mario Scheithauer | fd4f891 | 2023-03-17 09:58:56 +0100 | [diff] [blame] | 249 | /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */ |
| 250 | uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS]; |
| 251 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 252 | /* eMMC and SD */ |
| 253 | uint8_t ScsEmmcHs400Enabled; |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 254 | uint8_t ScsEmmcDdr50Enabled; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 255 | |
| 256 | /* Enable if SD Card Power Enable Signal is Active High */ |
| 257 | uint8_t SdCardPowerEnableActiveHigh; |
| 258 | |
Angel Pons | 035c6c8 | 2022-05-16 16:32:06 +0200 | [diff] [blame] | 259 | /* HECI related */ |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 260 | uint8_t Heci2Enable; |
| 261 | uint8_t Heci3Enable; |
| 262 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 263 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 264 | uint8_t eist_enable; |
| 265 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 266 | /* |
| 267 | * SerialIO device mode selection: |
| 268 | * PchSerialIoDisabled, |
| 269 | * PchSerialIoPci, |
| 270 | * PchSerialIoHidden, |
| 271 | * PchSerialIoLegacyUart, |
| 272 | * PchSerialIoSkipInit |
| 273 | */ |
| 274 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 275 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 276 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 277 | /* |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 278 | * UARTn Default DMA/PIO Mode Enable(1)/Disable(0): |
| 279 | */ |
| 280 | uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 281 | /* |
| 282 | * GSPIn Default Chip Enable(1)/Disable(0): |
| 283 | */ |
| 284 | uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 285 | /* |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 286 | * GSPIn Default Chip Select Mode: |
| 287 | * 0:Hardware Mode, |
| 288 | * 1:Software Mode |
| 289 | */ |
| 290 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 291 | /* |
| 292 | * GSPIn Default Chip Select State: |
| 293 | * 0: Low, |
| 294 | * 1: High |
| 295 | */ |
| 296 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 297 | /* |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 298 | * SerialIo I2C Pads Termination Config: |
| 299 | * 0x0:Hardware default, |
| 300 | * 0x1:None, |
| 301 | * 0x13:1kOhm weak pull-up, |
| 302 | * 0x15:5kOhm weak pull-up, |
| 303 | * 0x19:20kOhm weak pull-up |
| 304 | */ |
| 305 | uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * TraceHubMode config |
| 309 | * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 310 | */ |
| 311 | uint8_t TraceHubMode; |
| 312 | |
| 313 | /* Debug interface selection */ |
| 314 | enum { |
| 315 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 316 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
| 317 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 318 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
| 319 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 320 | } debug_interface_flag; |
| 321 | |
| 322 | /* GPIO SD card detect pin */ |
| 323 | unsigned int sdcard_cd_gpio; |
| 324 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 325 | /* |
| 326 | * Override GPIO PM configuration: |
| 327 | * 0: Use FSP default GPIO PM program, |
| 328 | * 1: coreboot to override GPIO PM program |
| 329 | */ |
| 330 | uint8_t gpio_override_pm; |
| 331 | |
| 332 | /* |
| 333 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 334 | * Bit 6-7: Reserved |
| 335 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 336 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 337 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 338 | * Bit 2: MISCCFG_GSXLCGEN |
| 339 | * Bit 1: MISCCFG_GPDPCGEN |
| 340 | * Bit 0: MISCCFG_GPDLCGEN |
| 341 | */ |
| 342 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 343 | |
| 344 | /* DP config */ |
| 345 | /* |
| 346 | * Port config |
| 347 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 348 | */ |
| 349 | uint8_t DdiPortAConfig; |
| 350 | uint8_t DdiPortBConfig; |
Michał Kopeć | 28daa6b | 2022-11-28 13:10:40 +0100 | [diff] [blame] | 351 | uint8_t DdiPortCConfig; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 352 | |
| 353 | /* Enable(1)/Disable(0) HPD */ |
| 354 | uint8_t DdiPortAHpd; |
| 355 | uint8_t DdiPortBHpd; |
| 356 | uint8_t DdiPortCHpd; |
| 357 | uint8_t DdiPort1Hpd; |
| 358 | uint8_t DdiPort2Hpd; |
| 359 | uint8_t DdiPort3Hpd; |
| 360 | uint8_t DdiPort4Hpd; |
| 361 | |
| 362 | /* Enable(1)/Disable(0) DDC */ |
| 363 | uint8_t DdiPortADdc; |
| 364 | uint8_t DdiPortBDdc; |
| 365 | uint8_t DdiPortCDdc; |
| 366 | uint8_t DdiPort1Ddc; |
| 367 | uint8_t DdiPort2Ddc; |
| 368 | uint8_t DdiPort3Ddc; |
| 369 | uint8_t DdiPort4Ddc; |
| 370 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 371 | /* Skip CPU replacement check |
| 372 | * 0: disable |
| 373 | * 1: enable |
| 374 | * Setting this option to skip CPU replacement check to avoid the forced MRC training |
| 375 | * for the platforms with soldered down SOC. |
| 376 | */ |
| 377 | uint8_t SkipCpuReplacementCheck; |
| 378 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 379 | struct { |
| 380 | bool fivr_config_en; |
| 381 | enum fivr_states v1p05_state; |
| 382 | enum fivr_states vnn_state; |
| 383 | enum fivr_states vnn_sx_state; |
| 384 | enum fivr_supported_voltage v1p05_rail; |
| 385 | enum fivr_supported_voltage vnn_rail; |
| 386 | /* Icc max for V1p05 rail in mA */ |
| 387 | unsigned int v1p05_icc_max_ma; |
| 388 | /* Vnn voltage in mV */ |
| 389 | unsigned int vnn_sx_mv; |
| 390 | /* Transition time in microseconds: */ |
| 391 | /* From low current mode voltage to high current mode voltage */ |
| 392 | unsigned int vcc_low_high_us; |
| 393 | /* From retention mode voltage to high current mode voltage */ |
| 394 | unsigned int vcc_ret_high_us; |
| 395 | /* From retention mode voltage to low current mode voltage */ |
| 396 | unsigned int vcc_ret_low_us; |
| 397 | /* From off(0V) to high current mode voltage */ |
| 398 | unsigned int vcc_off_high_us; |
| 399 | /* RFI spread spectrum, in 0.1% increment. Range: 0.0% to 10.0% (0-100). */ |
| 400 | unsigned int spread_spectrum; |
| 401 | } fivr; |
| 402 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 403 | /* |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 404 | * PCH power button override period. |
| 405 | * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s |
| 406 | */ |
| 407 | u8 PchPmPwrBtnOverridePeriod; |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 408 | |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 409 | /* GBE related (PCH & PSE) */ |
| 410 | /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 411 | enum tsn_gbe_link_speed PchTsnGbeLinkSpeed; |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 412 | enum tsn_gbe_link_speed PseTsnGbeLinkSpeed[MAX_PSE_TSN_PORTS]; |
| 413 | /* TSN GBE SGMII Support: Disable (0) / Enable (1) */ |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 414 | bool PchTsnGbeSgmiiEnable; |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 415 | bool PseTsnGbeSgmiiEnable[MAX_PSE_TSN_PORTS]; |
| 416 | /* TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */ |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 417 | bool PchTsnGbeMultiVcEnable; |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 418 | bool PseTsnGbeMultiVcEnable[MAX_PSE_TSN_PORTS]; |
| 419 | /* PSE TSN Phy Interface Type */ |
| 420 | enum tsn_phy_type PseTsnGbePhyType[MAX_PSE_TSN_PORTS]; |
Mario Scheithauer | dccdace | 2022-04-27 11:24:05 +0200 | [diff] [blame] | 421 | enum tsn_phy_irq_polarity pch_tsn_phy_irq_edge; |
| 422 | enum tsn_phy_irq_polarity pse_tsn_phy_irq_edge[MAX_PSE_TSN_PORTS]; |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 423 | |
| 424 | /* PSE related */ |
| 425 | /* |
| 426 | * PSE (Intel Programmable Services Engine) native pins and ownership |
| 427 | * assignment. If the device is configured as 'PSE owned', PSE will have |
| 428 | * full control of specific device and it will be hidden from coreboot |
| 429 | * and OS. If the device is configured as 'Host owned', the device will |
| 430 | * be visible to coreboot and OS as a PCI device, while PSE will still |
| 431 | * do some IP initialization and pin assignment works. |
| 432 | * |
| 433 | * PSE is still required during runtime to ensure any of PSE devices |
| 434 | * works properly. |
| 435 | */ |
| 436 | enum pse_device_ownership PseDmaOwn[3]; |
| 437 | enum pse_device_ownership PseUartOwn[6]; |
| 438 | enum pse_device_ownership PseHsuartOwn[4]; |
| 439 | enum pse_device_ownership PseQepOwn[4]; |
| 440 | enum pse_device_ownership PseI2cOwn[8]; |
| 441 | enum pse_device_ownership PseI2sOwn[2]; |
| 442 | enum pse_device_ownership PseSpiOwn[4]; |
| 443 | enum pse_device_ownership PseSpiCs0Own[4]; |
| 444 | enum pse_device_ownership PseSpiCs1Own[4]; |
| 445 | enum pse_device_ownership PseCanOwn[2]; |
| 446 | enum pse_device_ownership PsePwmOwn; |
| 447 | enum pse_device_ownership PseAdcOwn; |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 448 | enum pse_device_ownership PseGbeOwn[MAX_PSE_TSN_PORTS]; |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 449 | /* PSE devices sideband interrupt: Disable (0) / Enable (1) */ |
| 450 | bool PseDmaSbIntEn[3]; |
| 451 | bool PseUartSbIntEn[6]; |
| 452 | bool PseQepSbIntEn[4]; |
| 453 | bool PseI2cSbIntEn[8]; |
| 454 | bool PseI2sSbIntEn[2]; |
| 455 | bool PseSpiSbIntEn[4]; |
| 456 | bool PseCanSbIntEn[2]; |
| 457 | bool PseLh2PseSbIntEn; |
| 458 | bool PsePwmSbIntEn; |
| 459 | bool PseAdcSbIntEn; |
| 460 | /* PSE PWM native function: Disable (0) / Enable (1) */ |
| 461 | bool PsePwmPinEn[16]; |
| 462 | /* PSE Console Shell */ |
| 463 | bool PseShellEn; |
Christian Gmeiner | d8fd2ded | 2022-10-04 09:35:08 +0200 | [diff] [blame] | 464 | |
| 465 | /* |
| 466 | * DDR Frequency Limit |
| 467 | * |
| 468 | * Maximum Memory Frequency Selections in Mhz. |
| 469 | * Values: 1067, 1200, 1333, 1400, 1600, 1800, 1867, 2000, 2133, |
| 470 | * 2200, 2400, 2600, 2667, 2800, 2933, 3000, 3200, 3467, |
| 471 | * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. |
| 472 | */ |
| 473 | uint16_t max_dram_speed_mts; |
Werner Zeh | d03e896 | 2022-10-21 11:09:27 +0200 | [diff] [blame] | 474 | |
| 475 | /* Disable L1 prefetcher */ |
| 476 | bool L1_prefetcher_disable; |
Werner Zeh | adbdc5c | 2022-11-21 13:21:04 +0100 | [diff] [blame] | 477 | |
| 478 | /* Activate real time tuning according to the Real-Time Tuning Guide (doc #640979) */ |
| 479 | bool realtime_tuning_enable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 480 | }; |
| 481 | |
| 482 | typedef struct soc_intel_elkhartlake_config config_t; |
| 483 | |
| 484 | #endif |