Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 2 | |
Michael Niewöhner | 50a1072 | 2020-11-04 00:19:28 +0100 | [diff] [blame] | 3 | #include <device/device.h> |
Subrata Banik | 00b7533 | 2020-02-20 12:09:45 +0530 | [diff] [blame] | 4 | #include <intelblocks/cse.h> |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 5 | #include <intelblocks/smihandler.h> |
Subrata Banik | 00b7533 | 2020-02-20 12:09:45 +0530 | [diff] [blame] | 6 | #include <soc/soc_chip.h> |
Subrata Banik | e83d057 | 2018-02-20 11:49:45 +0530 | [diff] [blame] | 7 | #include <soc/pci_devs.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 8 | #include <soc/pm.h> |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 9 | |
Subrata Banik | e83d057 | 2018-02-20 11:49:45 +0530 | [diff] [blame] | 10 | /* |
| 11 | * Specific SOC SMI handler during ramstage finalize phase |
| 12 | * |
| 13 | * BIOS can't make CSME function disable as is due to POSTBOOT_SAI |
| 14 | * restriction in place from CNP chipset. Hence create SMI Handler to |
| 15 | * perform CSME function disabling logic during SMM mode. |
| 16 | */ |
| 17 | void smihandler_soc_at_finalize(void) |
| 18 | { |
Matt DeVillier | 575a2e5 | 2022-02-10 17:01:35 -0600 | [diff] [blame] | 19 | if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 20 | heci1_disable(); |
Subrata Banik | e83d057 | 2018-02-20 11:49:45 +0530 | [diff] [blame] | 21 | } |
| 22 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 23 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 24 | [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, |
| 25 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 26 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 27 | [GPE0_STS_BIT] = smihandler_southbridge_gpe0, |
| 28 | [GPIO_STS_BIT] = smihandler_southbridge_gpi, |
| 29 | [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, |
| 30 | [MCSMI_STS_BIT] = smihandler_southbridge_mc, |
Patrick Georgi | a7ec426 | 2020-03-11 16:31:59 +0100 | [diff] [blame] | 31 | #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 32 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
Patrick Georgi | a7ec426 | 2020-03-11 16:31:59 +0100 | [diff] [blame] | 33 | #endif |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 34 | [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, |
| 35 | [MONITOR_STS_BIT] = smihandler_southbridge_monitor, |
| 36 | }; |