Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 3 | #include <device/device.h> |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 4 | #include <intelblocks/pcie_rp.h> |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 5 | #include <soc/cpu.h> |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 6 | #include <soc/pci_devs.h> |
| 7 | #include <soc/pcie.h> |
| 8 | |
Tim Wawrzynczak | 40c9c8a | 2021-12-08 10:43:08 -0700 | [diff] [blame] | 9 | #define CPU_CPIE_VW_IDX_BASE 24 |
| 10 | |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 11 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 12 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 13 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 14 | { 0 } |
| 15 | }; |
| 16 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 17 | static const struct pcie_rp_group pch_m_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 18 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 19 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 2, .lcap_port_base = 1 }, |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 20 | { 0 } |
| 21 | }; |
| 22 | |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 23 | static const struct pcie_rp_group pch_s_rp_groups[] = { |
| 24 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 25 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, |
| 26 | { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, |
| 27 | { .slot = PCH_DEV_SLOT_PCIE_3, .count = 4, .lcap_port_base = 1 }, |
| 28 | { 0 } |
| 29 | }; |
| 30 | |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 31 | const struct pcie_rp_group *get_pch_pcie_rp_table(void) |
| 32 | { |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 33 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) |
| 34 | return pch_m_rp_groups; |
| 35 | |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 36 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) |
| 37 | return pch_s_rp_groups; |
| 38 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 39 | return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */ |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | /* |
| 43 | * ADL-P FSP define CPU RP as below: |
| 44 | * RP1: PEG60 : 0:6:0 : x4 CPU Slot |
| 45 | * RP2: PEG10 : 0:1:0 : x8 CPU Slot |
| 46 | * RP3: PEG62 : 0:6:2 : x4 CPU Slot |
| 47 | */ |
| 48 | static const struct pcie_rp_group cpu_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 49 | { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 }, |
| 50 | { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1, .lcap_port_base = 1 }, |
| 51 | { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1, .lcap_port_base = 1 }, |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 52 | { 0 } |
| 53 | }; |
| 54 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 55 | static const struct pcie_rp_group cpu_m_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 56 | { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 }, |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 57 | { 0 } |
| 58 | }; |
| 59 | |
| 60 | static const struct pcie_rp_group cpu_n_rp_groups[] = { |
| 61 | { 0 } |
| 62 | }; |
| 63 | |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 64 | static const struct pcie_rp_group cpu_s_rp_groups[] = { |
| 65 | { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 }, |
| 66 | { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 2, .lcap_port_base = 1 }, |
| 67 | { 0 } |
| 68 | }; |
| 69 | |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 70 | const struct pcie_rp_group *get_cpu_pcie_rp_table(void) |
| 71 | { |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 72 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) |
| 73 | return cpu_m_rp_groups; |
| 74 | |
| 75 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) |
| 76 | return cpu_n_rp_groups; |
| 77 | |
Michał Żygowski | 933a44b | 2022-04-15 18:15:44 +0200 | [diff] [blame] | 78 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) |
| 79 | return cpu_s_rp_groups; |
| 80 | |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 81 | return cpu_rp_groups; |
| 82 | } |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 83 | |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 84 | /* |
| 85 | * TBT's LCAP registers are returning port index which starts from 2 (Usually for other PCIe |
| 86 | * root ports index starts from 1). Thus keeping lcap_port_base 2 for TBT, so that coreboot's |
| 87 | * PCIe remapping logic can return correct index (0-based) |
| 88 | */ |
| 89 | |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 90 | static const struct pcie_rp_group tbt_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 91 | { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 2 }, |
MAULIK V VAGHELA | 3e4f28f | 2022-01-21 14:17:53 +0530 | [diff] [blame] | 92 | { 0 } |
| 93 | }; |
| 94 | |
| 95 | const struct pcie_rp_group *get_tbt_pcie_rp_table(void) |
| 96 | { |
| 97 | return tbt_rp_groups; |
| 98 | } |
| 99 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 100 | static bool is_part_of_group(const struct device *dev, |
| 101 | const struct pcie_rp_group *groups) |
| 102 | { |
| 103 | if (dev->path.type != DEVICE_PATH_PCI) |
| 104 | return false; |
| 105 | |
| 106 | const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); |
| 107 | const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); |
| 108 | const struct pcie_rp_group *group; |
| 109 | unsigned int i; |
| 110 | unsigned int fn; |
| 111 | |
| 112 | for (group = groups; group->count; ++group) { |
| 113 | for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { |
| 114 | if (slot_to_find == group->slot && fn_to_find == fn) |
| 115 | return true; |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | return false; |
| 120 | } |
| 121 | |
| 122 | enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) |
| 123 | { |
| 124 | if (is_part_of_group(dev, pch_lp_rp_groups)) |
| 125 | return PCIE_RP_PCH; |
| 126 | |
| 127 | if (CONFIG_MAX_CPU_ROOT_PORTS && is_part_of_group(dev, cpu_rp_groups)) |
| 128 | return PCIE_RP_CPU; |
| 129 | |
| 130 | return PCIE_RP_UNKNOWN; |
| 131 | } |
Tim Wawrzynczak | 40c9c8a | 2021-12-08 10:43:08 -0700 | [diff] [blame] | 132 | |
| 133 | int soc_get_cpu_rp_vw_idx(const struct device *dev) |
| 134 | { |
| 135 | if (dev->path.type != DEVICE_PATH_PCI) |
| 136 | return -1; |
| 137 | |
| 138 | switch (dev->path.pci.devfn) { |
| 139 | case SA_DEVFN_CPU_PCIE1_0: |
| 140 | return CPU_CPIE_VW_IDX_BASE; |
| 141 | case SA_DEVFN_CPU_PCIE6_0: |
| 142 | return CPU_CPIE_VW_IDX_BASE + 3; |
| 143 | case SA_DEVFN_CPU_PCIE6_2: |
| 144 | return CPU_CPIE_VW_IDX_BASE + 2; |
| 145 | default: |
| 146 | return -1; |
| 147 | } |
| 148 | } |