Martin Roth | 9231f0b | 2022-10-28 22:39:23 -0600 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 2 | ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 3 | subdirs-y += romstage |
| 4 | subdirs-y += ../../../cpu/intel/microcode |
| 5 | subdirs-y += ../../../cpu/intel/turbo |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 6 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 7 | # all (bootblock, verstage, romstage, postcar, ramstage) |
| 8 | all-y += gspi.c |
| 9 | all-y += i2c.c |
| 10 | all-y += pmutil.c |
| 11 | all-y += spi.c |
| 12 | all-y += uart.c |
| 13 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 14 | bootblock-y += bootblock/bootblock.c |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 15 | bootblock-y += bootblock/pch.c |
| 16 | bootblock-y += bootblock/report_platform.c |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 17 | bootblock-y += espi.c |
| 18 | bootblock-y += p2sb.c |
Reka Norman | e790f92 | 2022-04-06 20:33:54 +1000 | [diff] [blame] | 19 | bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 20 | |
Bora Guvendik | 9405049 | 2023-03-12 12:24:58 -0700 | [diff] [blame] | 21 | romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 22 | romstage-y += espi.c |
| 23 | romstage-y += meminit.c |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 24 | romstage-y += pcie_rp.c |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 25 | romstage-y += reset.c |
Subrata Banik | aab8bb2 | 2020-09-21 16:03:43 +0530 | [diff] [blame] | 26 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | ramstage-y += acpi.c |
| 28 | ramstage-y += chip.c |
| 29 | ramstage-y += cpu.c |
| 30 | ramstage-y += elog.c |
| 31 | ramstage-y += espi.c |
| 32 | ramstage-y += finalize.c |
| 33 | ramstage-y += fsp_params.c |
Tim Crawford | c6529c7 | 2022-11-01 11:42:28 -0600 | [diff] [blame] | 34 | ramstage-y += graphics.c |
Michał Żygowski | 9b0f169 | 2022-05-05 13:21:01 +0200 | [diff] [blame] | 35 | ramstage-y += hsphy.c |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 36 | ramstage-y += lockdown.c |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 37 | ramstage-y += p2sb.c |
Eric Lai | f8248f3 | 2020-12-31 11:43:29 +0800 | [diff] [blame] | 38 | ramstage-y += pcie_rp.c |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 39 | ramstage-y += pmc.c |
| 40 | ramstage-y += reset.c |
Michał Żygowski | 9df95d9 | 2022-04-08 17:02:35 +0200 | [diff] [blame] | 41 | ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 42 | ramstage-y += soundwire.c |
| 43 | ramstage-y += systemagent.c |
John | 848b425 | 2022-03-09 17:51:56 -0800 | [diff] [blame] | 44 | ramstage-y += tcss.c |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 45 | ramstage-y += vr_config.c |
Tim Wawrzynczak | 291b58f | 2020-11-10 10:25:04 -0700 | [diff] [blame] | 46 | ramstage-y += xhci.c |
Francois Toguo | cea4f92 | 2021-04-16 21:20:39 -0700 | [diff] [blame] | 47 | ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c |
Subrata Banik | aab8bb2 | 2020-09-21 16:03:43 +0530 | [diff] [blame] | 48 | |
Sugnan Prabhu S | f040f75 | 2021-03-26 10:58:49 +0530 | [diff] [blame] | 49 | smm-y += elog.c |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 50 | smm-y += p2sb.c |
| 51 | smm-y += pmutil.c |
| 52 | smm-y += smihandler.c |
| 53 | smm-y += uart.c |
Sugnan Prabhu S | f040f75 | 2021-03-26 10:58:49 +0530 | [diff] [blame] | 54 | smm-y += xhci.c |
Subrata Banik | aab8bb2 | 2020-09-21 16:03:43 +0530 | [diff] [blame] | 55 | |
Michał Kopeć | febaf2f | 2022-04-07 14:14:31 +0200 | [diff] [blame] | 56 | ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) |
| 57 | bootblock-y += gpio_pch_s.c |
| 58 | romstage-y += gpio_pch_s.c |
| 59 | ramstage-y += gpio_pch_s.c |
| 60 | smm-y += gpio_pch_s.c |
| 61 | verstage-y += gpio_pch_s.c |
| 62 | else |
| 63 | bootblock-y += gpio.c |
| 64 | romstage-y += gpio.c |
| 65 | ramstage-y += gpio.c |
| 66 | smm-y += gpio.c |
| 67 | verstage-y += gpio.c |
| 68 | endif |
| 69 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 70 | CPPFLAGS_common += -I$(src)/soc/intel/alderlake |
| 71 | CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 72 | |
Michał Żygowski | c651a27 | 2023-06-16 14:05:22 +0200 | [diff] [blame] | 73 | # Include the missing MemInfoHob.h from vendorcode |
| 74 | ifeq ($(CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S)$(CONFIG_FSP_TYPE_IOT),yy) |
| 75 | CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s |
| 76 | endif |
| 77 | |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 78 | ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) |
| 79 | # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples |
| 80 | # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples |
Nico Huber | 1dadb8c | 2023-07-07 20:19:12 +0200 | [diff] [blame] | 81 | # ADL-S/HX C0 and ADL-S H0 |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 82 | cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 |
Tim Crawford | 0b101fc | 2023-02-08 08:49:16 -0700 | [diff] [blame] | 83 | # RPL-S/HX B0 |
| 84 | cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 85 | # 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing |
Felix Singer | 52fb64b | 2023-06-03 06:12:57 +0200 | [diff] [blame] | 86 | else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) |
| 87 | cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 88 | else |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 89 | # 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples |
| 90 | # Missing 06-9a-02 ADL-P K0 |
Nico Huber | 1dadb8c | 2023-07-07 20:19:12 +0200 | [diff] [blame] | 91 | # ADL-P L0, ADL-P R0 and ADL-M R0 |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 92 | cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04 |
Tim Crawford | f1a4cff | 2023-03-03 11:58:18 -0700 | [diff] [blame] | 93 | # RPL-P/H J0, RPL-U Q0 |
| 94 | cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ba-02 |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 95 | endif |
Michał Żygowski | 6297df8 | 2022-06-30 16:22:35 +0200 | [diff] [blame] | 96 | |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 97 | ifeq ($(CONFIG_STITCH_ME_BIN),y) |
| 98 | |
Bernardo Perez Priego | aba1c13 | 2021-10-20 21:13:29 -0700 | [diff] [blame] | 99 | $(eval $(call cse_add_dummy_to_bp1_bp2,DLMP)) |
| 100 | $(eval $(call cse_add_dummy_to_bp1_bp2,IFPP)) |
| 101 | $(eval $(call cse_add_dummy_to_bp1_bp2,SBDT)) |
| 102 | $(eval $(call cse_add_decomp_to_bp1_bp2,RBEP)) |
| 103 | $(eval $(call cse_add_dummy_to_bp1_bp2,UFSP)) |
| 104 | $(eval $(call cse_add_dummy_to_bp1_bp2,UFSG)) |
Ravindra N | 0709218 | 2021-12-06 10:11:51 +0530 | [diff] [blame] | 105 | $(eval $(call cse_add_input_to_bp1_bp2,OEMP)) |
Bernardo Perez Priego | aba1c13 | 2021-10-20 21:13:29 -0700 | [diff] [blame] | 106 | $(eval $(call cse_add_input_to_bp1_bp2,PMCP)) |
| 107 | $(eval $(call cse_add_decomp,bp1,MFTP)) |
| 108 | $(eval $(call cse_add_decomp,bp2,FTPR)) |
| 109 | $(eval $(call cse_add_input_to_bp1_bp2,IOMP)) |
| 110 | $(eval $(call cse_add_input_to_bp1_bp2,NPHY)) |
| 111 | $(eval $(call cse_add_input_to_bp1_bp2,TBTP)) |
| 112 | $(eval $(call cse_add_input_to_bp1_bp2,PCHC)) |
| 113 | $(eval $(call cse_add_decomp,bp2,NFTP)) |
| 114 | $(eval $(call cse_add_dummy,bp2,ISHP)) |
| 115 | $(eval $(call cse_add_input,bp2,IUNP)) |
Furquan Shaikh | f888c68 | 2021-10-05 21:37:33 -0700 | [diff] [blame] | 116 | |
| 117 | endif |
| 118 | |
Michał Żygowski | 95be012 | 2022-10-29 21:32:54 +0200 | [diff] [blame] | 119 | ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y) |
| 120 | ifneq ($(call strip_quotes,$(CONFIG_HSPHY_FW_FILE)),) |
| 121 | |
| 122 | # Create the target HSPHY file that will be put into flashmap region. |
| 123 | # First goes the HSPHY size, then hash algorithm (3 - SHA384, default for now), |
| 124 | # the hash digest, padding to max digest size (SHA512 - 64 bytes) and at last the |
| 125 | # HSPHY firmware itself |
| 126 | $(obj)/hsphy_fw.bin: $(call strip_quotes,$(top)/$(CONFIG_HSPHY_FW_FILE)) |
| 127 | printf " HSPHY $(obj)/hsphy_fw.bin\n" |
| 128 | $(shell wc -c $< | awk '{print $$1}' | tr -d '\n' | xargs -0 printf '%08X' | \ |
| 129 | tac -rs .. | xxd -r -p > $@) |
| 130 | $(shell printf '%02X' 3 | xxd -r -p >> $@) |
| 131 | $(shell sha384sum $< | awk '{print $$1}' | tac -rs .. | xxd -r -p >> $@) |
| 132 | $(shell dd if=/dev/zero bs=1 count=16 2> /dev/null >> $@) |
| 133 | $(shell cat $< >> $@) |
| 134 | |
| 135 | add_hsphy_firmware: $(obj)/hsphy_fw.bin $(obj)/fmap.fmap $(obj)/coreboot.pre $(CBFSTOOL) |
| 136 | $(CBFSTOOL) $(obj)/coreboot.pre write -u -r HSPHY_FW -f $(obj)/hsphy_fw.bin |
| 137 | |
| 138 | $(call add_intermediate, add_hsphy_firmware) |
| 139 | |
| 140 | endif |
| 141 | endif |
| 142 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 143 | endif |