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Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08004
Stefan Reinauera48ca842015-04-04 01:58:28 +02005source "src/cpu/*/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +00006
Furquan Shaikhfd337812014-04-22 15:16:54 -07007if ARCH_X86
Stefan Reinauer704b5962010-08-30 17:53:13 +00009config CACHE_AS_RAM
Patrick Georgi39ec29c2009-08-27 12:10:50 +000010 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +000011 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +000012
Aaron Durbinbc17cde2017-04-07 15:20:14 -050013config NO_CAR_GLOBAL_MIGRATION
14 bool
15 default n
16 depends on CACHE_AS_RAM
17 help
18 This option is selected if there is no need to migrate CAR globals.
19 All stages which use CAR globals can directly access the variables
20 from their linked addresses.
Patrick Georgi0588d192009-08-12 15:00:51 +000022config DCACHE_RAM_BASE
23 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000024
26 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000027
Timothy Pearsonb5e46552015-06-02 13:47:36 -050028config DCACHE_BSP_STACK_SIZE
29 hex
Timothy Pearsonfb39f822015-06-02 20:25:03 -050031config DCACHE_BSP_STACK_SLUSH
32 hex
Timothy Pearsonb5e46552015-06-02 13:47:36 -050034config DCACHE_AP_STACK_SIZE
35 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000037config SMP
38 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000039 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000040 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000041 help
42 This option is used to enable certain functions to make coreboot
43 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000044
Kyösti Mälkki7dfe32c2012-02-14 10:39:17 +020045config AP_SIPI_VECTOR
46 hex
47 default 0xfffff000
48 help
49 This must equal address of ap_sipi_vector from bootblock build.
Patrick Georgi819c7d42012-03-31 13:08:12 +020050
Ronald G. Minnich149d6752009-10-01 23:22:50 +000051config MMX
52 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000053 help
54 Select MMX in your socket or model Kconfig if your CPU has MMX
55 streaming SIMD instructions. ROMCC can build more efficient
56 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000057
58config SSE
59 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000060 help
61 Select SSE in your socket or model Kconfig if your CPU has SSE
62 streaming SIMD instructions. ROMCC can build more efficient
63 code if it can spill to SSE (aka XMM) registers.
65config SSE2
66 bool
Myles Watson34261952010-03-19 02:33:40 +000067 default n
Aaron Durbinb1aa6112017-06-16 15:20:57 -050068 select SSE
Stefan Reinauera7acc512010-02-25 13:40:49 +000069 help
70 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
71 streaming SIMD instructions. Some parts of coreboot can be built
72 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000073
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000074endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050075
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060076config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050077 bool
78 default n
Martin Roth4c502692015-11-05 08:03:45 -070080config USES_MICROCODE_HEADER_FILES
81 def_bool n
83 help
84 This is selected by a board or chipset to set the default for the
85 microcode source choice to a list of external microcode headers
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050087choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010088 prompt "Include CPU microcode in CBFS" if ARCH_X86
Martin Roth4c502692015-11-05 08:03:45 -070089 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
Paul Menzelbdaeea52015-03-07 09:15:02 +010090 default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060091 default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050092
94 bool "Generate from tree"
95 help
96 Select this option if you want microcode updates to be assembled when
97 building coreboot and included in the final image as a separate CBFS
98 file. Microcode will not be hard-coded into ramstage.
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200100 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500101 time with cbfstool, if desired.
103 If unsure, select this option.
Martin Roth4c502692015-11-05 08:03:45 -0700105config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
106 bool "Include external microcode header files"
107 help
108 Select this option if you want to include external c header files
109 containing the CPU microcode. This will be included as a separate
110 file in CBFS.
112 A word of caution: only select this option if you are sure the
113 microcode that you have is newer than the microcode shipping with
114 coreboot.
116 The microcode file may be removed from the ROM image at a later
117 time with cbfstool, if desired.
119 If unsure, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500121config CPU_MICROCODE_CBFS_NONE
122 bool "Do not include microcode updates"
123 help
124 Select this option if you do not want CPU microcode included in CBFS.
125 Note that for some CPUs, the microcode is hard-coded into the source
126 tree and is not loaded from CBFS. In this case, microcode will still
127 be updated. There is a push to move all microcode to CBFS, but this
128 change is not implemented for all CPUs.
130 This option currently applies to:
131 - Intel SandyBridge/IvyBridge
132 - VIA Nano
134 Microcode may be added to the ROM image at a later time with cbfstool,
135 if desired.
137 If unsure, select "Generate from tree"
139 The GOOD:
140 Microcode updates intend to solve issues that have been discovered
141 after CPU production. The expected effect is that systems work as
142 intended with the updated microcode, but we have also seen cases where
143 issues were solved by not applying microcode updates.
145 The BAD:
146 Note that some operating system include these same microcode patches,
147 so you may need to also disable microcode updates in your operating
148 system for this option to have an effect.
150 The UGLY:
151 A word of CAUTION: some CPUs depend on microcode updates to function
152 correctly. Not updating the microcode may leave the CPU operating at
153 less than optimal performance, or may cause outright hangups.
154 There are CPUs where coreboot cannot properly initialize the CPU
155 without microcode updates
156 For example, if running with the factory microcode, some Intel
157 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
158 will hang when changing the frequency.
160 Make sure you have a way of flashing the ROM externally before
161 selecting this option.
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100164
Timothy Pearson24e6d042015-10-08 16:58:58 -0500165config CPU_MICROCODE_MULTIPLE_FILES
166 bool
167 default n
169 help
170 Select this option to install separate microcode container files into
171 CBFS instead of using the traditional monolithic microcode file format.
Martin Roth4c502692015-11-05 08:03:45 -0700172
174 string "List of space separated microcode header files with the path"
176 help
177 A list of one or more microcode header files with path from the
178 coreboot directory. These should be separated by spaces.
Martin Roth3eb65ec2016-08-30 16:21:53 -0600179
181 string "Microcode binary path and filename"
183 default ""
184 help
185 Some platforms have microcode in the blobs directory, and these can
186 be hardcoded in the makefiles. For platforms with microcode
187 binaries that aren't in the makefile, set this option to pull
188 in the microcode.
190 This should contain the full path of the file for one or more
191 microcode binary files to include, separated by spaces.
193 If unsure, leave this blank.