Jonathan Zhang | 6d27778 | 2020-06-09 17:56:53 -0700 | [diff] [blame] | 1 | /** @file |
| 2 | Platform TPM Profile Specification definition for TPM2.0. |
| 3 | It covers both FIFO and CRB interface. |
| 4 | |
| 5 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR> |
| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 7 | |
| 8 | **/ |
| 9 | |
| 10 | #ifndef _TPM_PTP_H_ |
| 11 | #define _TPM_PTP_H_ |
| 12 | |
| 13 | // |
| 14 | // PTP FIFO definition |
| 15 | // |
| 16 | |
| 17 | // |
| 18 | // Set structure alignment to 1-byte |
| 19 | // |
| 20 | #pragma pack (1) |
| 21 | |
| 22 | // |
| 23 | // Register set map as specified in PTP specification Chapter 5 |
| 24 | // |
| 25 | typedef struct { |
| 26 | /// |
| 27 | /// Used to gain ownership for this particular port. |
| 28 | /// |
| 29 | UINT8 Access; // 0 |
| 30 | UINT8 Reserved1[7]; // 1 |
| 31 | /// |
| 32 | /// Controls interrupts. |
| 33 | /// |
| 34 | UINT32 IntEnable; // 8 |
| 35 | /// |
| 36 | /// SIRQ vector to be used by the TPM. |
| 37 | /// |
| 38 | UINT8 IntVector; // 0ch |
| 39 | UINT8 Reserved2[3]; // 0dh |
| 40 | /// |
| 41 | /// What caused interrupt. |
| 42 | /// |
| 43 | UINT32 IntSts; // 10h |
| 44 | /// |
| 45 | /// Shows which interrupts are supported by that particular TPM. |
| 46 | /// |
| 47 | UINT32 InterfaceCapability;// 14h |
| 48 | /// |
| 49 | /// Status Register. Provides status of the TPM. |
| 50 | /// |
| 51 | UINT8 Status; // 18h |
| 52 | /// |
| 53 | /// Number of consecutive writes that can be done to the TPM. |
| 54 | /// |
| 55 | UINT16 BurstCount; // 19h |
| 56 | /// |
| 57 | /// Additional Status Register. |
| 58 | /// |
| 59 | UINT8 StatusEx; // 1Bh |
| 60 | UINT8 Reserved3[8]; |
| 61 | /// |
| 62 | /// Read or write FIFO, depending on transaction. |
| 63 | /// |
| 64 | UINT32 DataFifo; // 24h |
| 65 | UINT8 Reserved4[8]; // 28h |
| 66 | /// |
| 67 | /// Used to identify the Interface types supported by the TPM. |
| 68 | /// |
| 69 | UINT32 InterfaceId; // 30h |
| 70 | UINT8 Reserved5[0x4c]; // 34h |
| 71 | /// |
| 72 | /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write) |
| 73 | /// |
| 74 | UINT32 XDataFifo; // 80h |
| 75 | UINT8 Reserved6[0xe7c]; // 84h |
| 76 | /// |
| 77 | /// Vendor ID |
| 78 | /// |
| 79 | UINT16 Vid; // 0f00h |
| 80 | /// |
| 81 | /// Device ID |
| 82 | /// |
| 83 | UINT16 Did; // 0f02h |
| 84 | /// |
| 85 | /// Revision ID |
| 86 | /// |
| 87 | UINT8 Rid; // 0f04h |
| 88 | UINT8 Reserved[0xfb]; // 0f05h |
| 89 | } PTP_FIFO_REGISTERS; |
| 90 | |
| 91 | // |
| 92 | // Restore original structure alignment |
| 93 | // |
| 94 | #pragma pack () |
| 95 | |
| 96 | // |
| 97 | // Define pointer types used to access TIS registers on PC |
| 98 | // |
| 99 | typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR; |
| 100 | |
| 101 | // |
| 102 | // Define bits of FIFO Interface Identifier Register |
| 103 | // |
| 104 | typedef union { |
| 105 | struct { |
| 106 | UINT32 InterfaceType:4; |
| 107 | UINT32 InterfaceVersion:4; |
| 108 | UINT32 CapLocality:1; |
| 109 | UINT32 Reserved1:2; |
| 110 | UINT32 CapDataXferSizeSupport:2; |
| 111 | UINT32 CapFIFO:1; |
| 112 | UINT32 CapCRB:1; |
| 113 | UINT32 CapIFRes:2; |
| 114 | UINT32 InterfaceSelector:2; |
| 115 | UINT32 IntfSelLock:1; |
| 116 | UINT32 Reserved2:4; |
| 117 | UINT32 Reserved3:8; |
| 118 | } Bits; |
| 119 | UINT32 Uint32; |
| 120 | } PTP_FIFO_INTERFACE_IDENTIFIER; |
| 121 | |
| 122 | // |
| 123 | // Define bits of FIFO Interface Capability Register |
| 124 | // |
| 125 | typedef union { |
| 126 | struct { |
| 127 | UINT32 DataAvailIntSupport:1; |
| 128 | UINT32 StsValidIntSupport:1; |
| 129 | UINT32 LocalityChangeIntSupport:1; |
| 130 | UINT32 InterruptLevelHigh:1; |
| 131 | UINT32 InterruptLevelLow:1; |
| 132 | UINT32 InterruptEdgeRising:1; |
| 133 | UINT32 InterruptEdgeFalling:1; |
| 134 | UINT32 CommandReadyIntSupport:1; |
| 135 | UINT32 BurstCountStatic:1; |
| 136 | UINT32 DataTransferSizeSupport:2; |
| 137 | UINT32 Reserved:17; |
| 138 | UINT32 InterfaceVersion:3; |
| 139 | UINT32 Reserved2:1; |
| 140 | } Bits; |
| 141 | UINT32 Uint32; |
| 142 | } PTP_FIFO_INTERFACE_CAPABILITY; |
| 143 | |
| 144 | /// |
| 145 | /// InterfaceVersion |
| 146 | /// |
| 147 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0 |
| 148 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2 |
| 149 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3 |
| 150 | |
| 151 | |
| 152 | // |
| 153 | // Define bits of ACCESS and STATUS registers |
| 154 | // |
| 155 | |
| 156 | /// |
| 157 | /// This bit is a 1 to indicate that the other bits in this register are valid. |
| 158 | /// |
| 159 | #define PTP_FIFO_VALID BIT7 |
| 160 | /// |
| 161 | /// Indicate that this locality is active. |
| 162 | /// |
| 163 | #define PTP_FIFO_ACC_ACTIVE BIT5 |
| 164 | /// |
| 165 | /// Set to 1 to indicate that this locality had the TPM taken away while |
| 166 | /// this locality had the TIS_PC_ACC_ACTIVE bit set. |
| 167 | /// |
| 168 | #define PTP_FIFO_ACC_SEIZED BIT4 |
| 169 | /// |
| 170 | /// Set to 1 to indicate that TPM MUST reset the |
| 171 | /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the |
| 172 | /// locality that is writing this bit. |
| 173 | /// |
| 174 | #define PTP_FIFO_ACC_SEIZE BIT3 |
| 175 | /// |
| 176 | /// When this bit is 1, another locality is requesting usage of the TPM. |
| 177 | /// |
| 178 | #define PTP_FIFO_ACC_PENDIND BIT2 |
| 179 | /// |
| 180 | /// Set to 1 to indicate that this locality is requesting to use TPM. |
| 181 | /// |
| 182 | #define PTP_FIFO_ACC_RQUUSE BIT1 |
| 183 | /// |
| 184 | /// A value of 1 indicates that a T/OS has not been established on the platform |
| 185 | /// |
| 186 | #define PTP_FIFO_ACC_ESTABLISH BIT0 |
| 187 | |
| 188 | /// |
| 189 | /// This field indicates that STS_DATA and STS_EXPECT are valid |
| 190 | /// |
| 191 | #define PTP_FIFO_STS_VALID BIT7 |
| 192 | /// |
| 193 | /// When this bit is 1, TPM is in the Ready state, |
| 194 | /// indicating it is ready to receive a new command. |
| 195 | /// |
| 196 | #define PTP_FIFO_STS_READY BIT6 |
| 197 | /// |
| 198 | /// Write a 1 to this bit to cause the TPM to execute that command. |
| 199 | /// |
| 200 | #define PTP_FIFO_STS_GO BIT5 |
| 201 | /// |
| 202 | /// This bit indicates that the TPM has data available as a response. |
| 203 | /// |
| 204 | #define PTP_FIFO_STS_DATA BIT4 |
| 205 | /// |
| 206 | /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command. |
| 207 | /// |
| 208 | #define PTP_FIFO_STS_EXPECT BIT3 |
| 209 | /// |
| 210 | /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command. |
| 211 | /// |
| 212 | #define PTP_FIFO_STS_SELFTEST_DONE BIT2 |
| 213 | /// |
| 214 | /// Writes a 1 to this bit to force the TPM to re-send the response. |
| 215 | /// |
| 216 | #define PTP_FIFO_STS_RETRY BIT1 |
| 217 | |
| 218 | /// |
| 219 | /// TPM Family Identifier. |
| 220 | /// 00: TPM 1.2 Family |
| 221 | /// 01: TPM 2.0 Family |
| 222 | /// |
| 223 | #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) |
| 224 | #define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2) |
| 225 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0) |
| 226 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) |
| 227 | /// |
| 228 | /// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED. |
| 229 | /// A write of 1 after dataAvail and before tpmGo is ignored by the TPM. |
| 230 | /// |
| 231 | #define PTP_FIFO_STS_EX_CANCEL BIT0 |
| 232 | |
| 233 | |
| 234 | // |
| 235 | // PTP CRB definition |
| 236 | // |
| 237 | |
| 238 | // |
| 239 | // Set structure alignment to 1-byte |
| 240 | // |
| 241 | #pragma pack (1) |
| 242 | |
| 243 | // |
| 244 | // Register set map as specified in PTP specification Chapter 5 |
| 245 | // |
| 246 | typedef struct { |
| 247 | /// |
| 248 | /// Used to determine current state of Locality of the TPM. |
| 249 | /// |
| 250 | UINT32 LocalityState; // 0 |
| 251 | UINT8 Reserved1[4]; // 4 |
| 252 | /// |
| 253 | /// Used to gain control of the TPM by this Locality. |
| 254 | /// |
| 255 | UINT32 LocalityControl; // 8 |
| 256 | /// |
| 257 | /// Used to determine whether Locality has been granted or Seized. |
| 258 | /// |
| 259 | UINT32 LocalityStatus; // 0ch |
| 260 | UINT8 Reserved2[0x20]; // 10h |
| 261 | /// |
| 262 | /// Used to identify the Interface types supported by the TPM. |
| 263 | /// |
| 264 | UINT32 InterfaceId; // 30h |
| 265 | /// |
| 266 | /// Vendor ID |
| 267 | /// |
| 268 | UINT16 Vid; // 34h |
| 269 | /// |
| 270 | /// Device ID |
| 271 | /// |
| 272 | UINT16 Did; // 36h |
| 273 | /// |
| 274 | /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability. |
| 275 | /// |
| 276 | UINT64 CrbControlExtension; // 38h |
| 277 | /// |
| 278 | /// Register used to initiate transactions for the CRB interface. |
| 279 | /// |
| 280 | UINT32 CrbControlRequest; // 40h |
| 281 | /// |
| 282 | /// Register used by the TPM to provide status of the CRB interface. |
| 283 | /// |
| 284 | UINT32 CrbControlStatus; // 44h |
| 285 | /// |
| 286 | /// Register used by software to cancel command processing. |
| 287 | /// |
| 288 | UINT32 CrbControlCancel; // 48h |
| 289 | /// |
| 290 | /// Register used to indicate presence of command or response data in the CRB buffer. |
| 291 | /// |
| 292 | UINT32 CrbControlStart; // 4Ch |
| 293 | /// |
| 294 | /// Register used to configure and respond to interrupts. |
| 295 | /// |
| 296 | UINT32 CrbInterruptEnable; // 50h |
| 297 | UINT32 CrbInterruptStatus; // 54h |
| 298 | /// |
| 299 | /// Size of the Command buffer. |
| 300 | /// |
| 301 | UINT32 CrbControlCommandSize; // 58h |
| 302 | /// |
| 303 | /// Command buffer start address |
| 304 | /// |
| 305 | UINT32 CrbControlCommandAddressLow; // 5Ch |
| 306 | UINT32 CrbControlCommandAddressHigh; // 60h |
| 307 | /// |
| 308 | /// Size of the Response buffer |
| 309 | /// |
| 310 | UINT32 CrbControlResponseSize; // 64h |
| 311 | /// |
| 312 | /// Address of the start of the Response buffer |
| 313 | /// |
| 314 | UINT64 CrbControlResponseAddrss; // 68h |
| 315 | UINT8 Reserved4[0x10]; // 70h |
| 316 | /// |
| 317 | /// Command/Response Data may be defined as large as 3968 (0xF80). |
| 318 | /// |
| 319 | UINT8 CrbDataBuffer[0xF80]; // 80h |
| 320 | } PTP_CRB_REGISTERS; |
| 321 | |
| 322 | // |
| 323 | // Define pointer types used to access CRB registers on PTP |
| 324 | // |
| 325 | typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR; |
| 326 | |
| 327 | // |
| 328 | // Define bits of CRB Interface Identifier Register |
| 329 | // |
| 330 | typedef union { |
| 331 | struct { |
| 332 | UINT32 InterfaceType:4; |
| 333 | UINT32 InterfaceVersion:4; |
| 334 | UINT32 CapLocality:1; |
| 335 | UINT32 CapCRBIdleBypass:1; |
| 336 | UINT32 Reserved1:1; |
| 337 | UINT32 CapDataXferSizeSupport:2; |
| 338 | UINT32 CapFIFO:1; |
| 339 | UINT32 CapCRB:1; |
| 340 | UINT32 CapIFRes:2; |
| 341 | UINT32 InterfaceSelector:2; |
| 342 | UINT32 IntfSelLock:1; |
| 343 | UINT32 Reserved2:4; |
| 344 | UINT32 Rid:8; |
| 345 | } Bits; |
| 346 | UINT32 Uint32; |
| 347 | } PTP_CRB_INTERFACE_IDENTIFIER; |
| 348 | |
| 349 | /// |
| 350 | /// InterfaceType |
| 351 | /// |
| 352 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0 |
| 353 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1 |
| 354 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF |
| 355 | |
| 356 | /// |
| 357 | /// InterfaceVersion |
| 358 | /// |
| 359 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0 |
| 360 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1 |
| 361 | |
| 362 | /// |
| 363 | /// InterfaceSelector |
| 364 | /// |
| 365 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0 |
| 366 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1 |
| 367 | |
| 368 | // |
| 369 | // Define bits of Locality State Register |
| 370 | // |
| 371 | |
| 372 | /// |
| 373 | /// This bit indicates whether all other bits of this register contain valid values, if it is a 1. |
| 374 | /// |
| 375 | #define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7 |
| 376 | |
| 377 | /// |
| 378 | /// 000 - Locality 0 |
| 379 | /// 001 - Locality 1 |
| 380 | /// 010 - Locality 2 |
| 381 | /// 011 - Locality 3 |
| 382 | /// 100 - Locality 4 |
| 383 | /// |
| 384 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) |
| 385 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0) |
| 386 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) |
| 387 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3) |
| 388 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) |
| 389 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4) |
| 390 | |
| 391 | /// |
| 392 | /// A 0 indicates to the host that no locality is assigned. |
| 393 | /// A 1 indicates a locality has been assigned. |
| 394 | /// |
| 395 | #define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1 |
| 396 | |
| 397 | /// |
| 398 | /// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End |
| 399 | /// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1. |
| 400 | /// |
| 401 | #define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0 |
| 402 | |
| 403 | // |
| 404 | // Define bits of Locality Control Register |
| 405 | // |
| 406 | |
| 407 | /// |
| 408 | /// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4. |
| 409 | /// |
| 410 | #define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3 |
| 411 | |
| 412 | /// |
| 413 | /// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality. |
| 414 | /// |
| 415 | #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2 |
| 416 | |
| 417 | /// |
| 418 | /// Writes (1): The active Locality is done with the TPM. |
| 419 | /// |
| 420 | #define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1 |
| 421 | |
| 422 | /// |
| 423 | /// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm. |
| 424 | /// |
| 425 | #define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0 |
| 426 | |
| 427 | // |
| 428 | // Define bits of Locality Status Register |
| 429 | // |
| 430 | |
| 431 | /// |
| 432 | /// 0: A higher locality has not initiated a Seize arbitration process. |
| 433 | /// 1: A higher locality has Seized the TPM from this locality. |
| 434 | /// |
| 435 | #define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1 |
| 436 | |
| 437 | /// |
| 438 | /// 0: Locality has not been granted to the TPM. |
| 439 | /// 1: Locality has been granted access to the TPM |
| 440 | /// |
| 441 | #define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0 |
| 442 | |
| 443 | // |
| 444 | // Define bits of CRB Control Area Request Register |
| 445 | // |
| 446 | |
| 447 | /// |
| 448 | /// Used by Software to indicate transition the TPM to and from the Idle state |
| 449 | /// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle |
| 450 | /// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state. |
| 451 | /// TPM SHALL complete this transition within TIMEOUT_C. |
| 452 | /// |
| 453 | #define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1 |
| 454 | |
| 455 | /// |
| 456 | /// Used by Software to request the TPM transition to the Ready State. |
| 457 | /// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command. |
| 458 | /// 0: Cleared to 0 by TPM to acknowledge the request. |
| 459 | /// TPM SHALL complete this transition within TIMEOUT_C. |
| 460 | /// |
| 461 | #define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0 |
| 462 | |
| 463 | // |
| 464 | // Define bits of CRB Control Area Status Register |
| 465 | // |
| 466 | |
| 467 | /// |
| 468 | /// Used by TPM to indicate it is in the Idle State |
| 469 | /// 1: Set by TPM when in the Idle State |
| 470 | /// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State. |
| 471 | /// SHALL be cleared by TIMEOUT_C. |
| 472 | /// |
| 473 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1 |
| 474 | |
| 475 | /// |
| 476 | /// Used by the TPM to indicate current status. |
| 477 | /// 1: Set by TPM to indicate a FATAL Error |
| 478 | /// 0: Indicates TPM is operational |
| 479 | /// |
| 480 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0 |
| 481 | |
| 482 | // |
| 483 | // Define bits of CRB Control Cancel Register |
| 484 | // |
| 485 | |
| 486 | /// |
| 487 | /// Used by software to cancel command processing Reads return correct value |
| 488 | /// Writes (0000 0001h): Cancel a command |
| 489 | /// Writes (0000 0000h): Clears field when command has been cancelled |
| 490 | /// |
| 491 | #define PTP_CRB_CONTROL_CANCEL BIT0 |
| 492 | |
| 493 | // |
| 494 | // Define bits of CRB Control Start Register |
| 495 | // |
| 496 | |
| 497 | /// |
| 498 | /// When set by software, indicates a command is ready for processing. |
| 499 | /// Writes (0000 0001h): TPM transitions to Command Execution |
| 500 | /// Writes (0000 0000h): TPM clears this field and transitions to Command Completion |
| 501 | /// |
| 502 | #define PTP_CRB_CONTROL_START BIT0 |
| 503 | |
| 504 | // |
| 505 | // Restore original structure alignment |
| 506 | // |
| 507 | #pragma pack () |
| 508 | |
| 509 | // |
| 510 | // Default TimeOut value |
| 511 | // |
| 512 | #define PTP_TIMEOUT_A (750 * 1000) // 750ms |
| 513 | #define PTP_TIMEOUT_B (2000 * 1000) // 2s |
| 514 | #define PTP_TIMEOUT_C (200 * 1000) // 200ms |
| 515 | #define PTP_TIMEOUT_D (30 * 1000) // 30ms |
| 516 | |
| 517 | #endif |