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Jonathan Zhang6d277782020-06-09 17:56:53 -07001/** @file
2 Support for PCI 3.0 standard.
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7**/
8
9#ifndef __PCI30_H__
10#define __PCI30_H__
11
12
13#include <IndustryStandard/Pci23.h>
14
15///
16/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
17///
18///@{
19#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
20#define PCI_IF_MASS_STORAGE_SATA 0x00
21#define PCI_IF_MASS_STORAGE_AHCI 0x01
22///@}
23
24///
25/// PCI_CLASS_WIRELESS, Base Class 0Dh.
26///
27///@{
28#define PCI_SUBCLASS_ETHERNET_80211A 0x20
29#define PCI_SUBCLASS_ETHERNET_80211B 0x21
30///@}
31
32/**
33 Macro that checks whether device is a SATA controller.
34
35 @param _p Specified device.
36
37 @retval TRUE Device is a SATA controller.
38 @retval FALSE Device is not a SATA controller.
39
40**/
41#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
42
43///
44/// PCI Capability List IDs and records
45///
46#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
47
48#pragma pack(1)
49
50///
51/// PCI Data Structure Format
52/// Section 5.1.2, PCI Firmware Specification, Revision 3.0
53///
54typedef struct {
55 UINT32 Signature; ///< "PCIR"
56 UINT16 VendorId;
57 UINT16 DeviceId;
58 UINT16 DeviceListOffset;
59 UINT16 Length;
60 UINT8 Revision;
61 UINT8 ClassCode[3];
62 UINT16 ImageLength;
63 UINT16 CodeRevision;
64 UINT8 CodeType;
65 UINT8 Indicator;
66 UINT16 MaxRuntimeImageLength;
67 UINT16 ConfigUtilityCodeHeaderOffset;
68 UINT16 DMTFCLPEntryPointOffset;
69} PCI_3_0_DATA_STRUCTURE;
70
71#pragma pack()
72
73#endif