Angel Pons | 32abdd6 | 2020-04-05 15:47:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 5 | #include <pc80/isa-dma.h> |
| 6 | #include <pc80/i8259.h> |
| 7 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 9 | #include <arch/ioapic.h> |
| 10 | #include <intelblocks/itss.h> |
| 11 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 3d152ac | 2018-10-31 23:08:14 +0530 | [diff] [blame] | 12 | #include <soc/espi.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | #include <soc/iomap.h> |
Subrata Banik | 8ad5a62 | 2018-11-14 15:50:03 +0530 | [diff] [blame] | 14 | #include <soc/irq.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pcr_ids.h> |
Subrata Banik | df29d23 | 2019-07-05 16:00:38 +0530 | [diff] [blame] | 17 | #include <soc/soc_chip.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 18 | |
Patrick Georgi | 40b8f01 | 2021-05-12 14:52:12 +0200 | [diff] [blame] | 19 | void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 20 | { |
Furquan Shaikh | e4f7e04 | 2020-12-23 14:11:00 -0800 | [diff] [blame] | 21 | const config_t *config = config_of_soc(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 22 | |
| 23 | gen_io_dec[0] = config->gen1_dec; |
| 24 | gen_io_dec[1] = config->gen2_dec; |
| 25 | gen_io_dec[2] = config->gen3_dec; |
| 26 | gen_io_dec[3] = config->gen4_dec; |
| 27 | } |
| 28 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 29 | #if ENV_RAMSTAGE |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 30 | void lpc_soc_init(struct device *dev) |
| 31 | { |
| 32 | /* Legacy initialization */ |
| 33 | isa_dma_init(); |
| 34 | pch_misc_init(); |
| 35 | |
Subrata Banik | 3d152ac | 2018-10-31 23:08:14 +0530 | [diff] [blame] | 36 | /* Enable CLKRUN_EN for power gating ESPI */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 37 | lpc_enable_pci_clk_cntl(); |
| 38 | |
Subrata Banik | 3d152ac | 2018-10-31 23:08:14 +0530 | [diff] [blame] | 39 | /* Set ESPI Serial IRQ mode */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 40 | if (CONFIG(SERIRQ_CONTINUOUS_MODE)) |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 41 | lpc_set_serirq_mode(SERIRQ_CONTINUOUS); |
| 42 | else |
| 43 | lpc_set_serirq_mode(SERIRQ_QUIET); |
| 44 | |
| 45 | /* Interrupt configuration */ |
Subrata Banik | 1366e44 | 2020-09-29 13:55:50 +0530 | [diff] [blame] | 46 | pch_enable_ioapic(); |
Subrata Banik | 78463a7 | 2020-09-29 14:28:09 +0530 | [diff] [blame] | 47 | pch_pirq_init(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 48 | setup_i8259(); |
| 49 | i8259_configure_irq_trigger(9, 1); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 50 | } |
| 51 | |
Subrata Banik | 3d152ac | 2018-10-31 23:08:14 +0530 | [diff] [blame] | 52 | /* Fill up ESPI IO resource structure inside SoC directory */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 53 | void pch_lpc_soc_fill_io_resources(struct device *dev) |
| 54 | { |
| 55 | /* |
| 56 | * PMC pci device gets hidden from PCI bus due to Silicon |
| 57 | * policy hence bind ACPI BASE aka ABASE (offset 0x20) with |
Subrata Banik | 3d152ac | 2018-10-31 23:08:14 +0530 | [diff] [blame] | 58 | * ESPI IO resources to ensure that ABASE falls under PCI reserved |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 59 | * IO memory range. |
| 60 | * |
| 61 | * Note: Don't add any more resource with same offset 0x20 |
| 62 | * under this device space. |
| 63 | */ |
| 64 | pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, |
| 65 | ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | |
| 66 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); |
| 67 | } |
| 68 | |
| 69 | #endif |