Angel Pons | 32abdd6 | 2020-04-05 15:47:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 3 | #include <device/pci.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 4 | #include <cpu/x86/mp.h> |
| 5 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 6 | #include <cpu/intel/smm_reloc.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 7 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame] | 8 | #include <cpu/intel/common/common.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 9 | #include <fsp/api.h> |
| 10 | #include <intelblocks/cpulib.h> |
| 11 | #include <intelblocks/mp_init.h> |
Aamir Bohra | 34508cd | 2018-04-19 18:03:46 +0530 | [diff] [blame] | 12 | #include <intelblocks/msr.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | #include <soc/cpu.h> |
| 14 | #include <soc/msr.h> |
| 15 | #include <soc/pci_devs.h> |
Subrata Banik | df29d23 | 2019-07-05 16:00:38 +0530 | [diff] [blame] | 16 | #include <soc/soc_chip.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 17 | #include <types.h> |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 18 | |
Subrata Banik | 56ab8e2 | 2022-01-07 13:40:19 +0000 | [diff] [blame] | 19 | bool cpu_soc_is_in_untrusted_mode(void) |
| 20 | { |
| 21 | msr_t msr; |
| 22 | |
| 23 | msr = rdmsr(MSR_BIOS_DONE); |
| 24 | return !!(msr.lo & ENABLE_IA_UNTRUSTED); |
| 25 | } |
| 26 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 27 | static void soc_fsp_load(void) |
| 28 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 29 | fsps_load(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 30 | } |
| 31 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 32 | static void configure_misc(void) |
| 33 | { |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 34 | msr_t msr; |
| 35 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 36 | config_t *conf = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 37 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 38 | msr = rdmsr(IA32_MISC_ENABLE); |
| 39 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 40 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Matt Delco | 54e9894 | 2020-03-09 12:41:09 -0700 | [diff] [blame] | 41 | wrmsr(IA32_MISC_ENABLE, msr); |
| 42 | |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 43 | /* Set EIST status */ |
| 44 | cpu_set_eist(conf->eist_enable); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 45 | |
| 46 | /* Disable Thermal interrupts */ |
| 47 | msr.lo = 0; |
| 48 | msr.hi = 0; |
| 49 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 50 | |
| 51 | /* Enable package critical interrupt only */ |
| 52 | msr.lo = 1 << 4; |
| 53 | msr.hi = 0; |
| 54 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 55 | |
| 56 | /* Enable PROCHOT */ |
| 57 | msr = rdmsr(MSR_POWER_CTL); |
Angel Pons | 4d794bd | 2021-10-11 14:00:54 +0200 | [diff] [blame] | 58 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 59 | msr.lo |= (1 << 23); /* Lock it */ |
| 60 | wrmsr(MSR_POWER_CTL, msr); |
| 61 | } |
| 62 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 63 | static void configure_c_states(void) |
| 64 | { |
| 65 | msr_t msr; |
| 66 | |
| 67 | /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ |
| 68 | msr.hi = 0; |
| 69 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| 70 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
| 71 | |
| 72 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ |
| 73 | msr.hi = 0; |
| 74 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| 75 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
| 76 | |
| 77 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 78 | msr.hi = 0; |
| 79 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
| 80 | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 81 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
| 82 | |
| 83 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 84 | msr.hi = 0; |
| 85 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
| 86 | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 87 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 88 | |
| 89 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 90 | msr.hi = 0; |
| 91 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
| 92 | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 93 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 94 | } |
| 95 | |
| 96 | /* All CPUs including BSP will run the following function. */ |
| 97 | void soc_core_init(struct device *cpu) |
| 98 | { |
| 99 | /* Clear out pending MCEs */ |
| 100 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 101 | * of these banks are core vs package scope. For now every CPU clears |
| 102 | * every bank. */ |
Subrata Banik | f91344c | 2019-05-06 19:23:26 +0530 | [diff] [blame] | 103 | mca_configure(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 104 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 105 | enable_lapic_tpr(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 106 | |
| 107 | /* Configure c-state interrupt response time */ |
| 108 | configure_c_states(); |
| 109 | |
| 110 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 111 | configure_misc(); |
| 112 | |
Aamir Bohra | 34508cd | 2018-04-19 18:03:46 +0530 | [diff] [blame] | 113 | enable_pm_timer_emulation(); |
| 114 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 115 | /* Enable Direct Cache Access */ |
| 116 | configure_dca_cap(); |
| 117 | |
| 118 | /* Set energy policy */ |
| 119 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 120 | |
| 121 | /* Enable Turbo */ |
| 122 | enable_turbo(); |
| 123 | } |
| 124 | |
| 125 | static void per_cpu_smm_trigger(void) |
| 126 | { |
| 127 | /* Relocate the SMM handler. */ |
| 128 | smm_relocate(); |
| 129 | } |
| 130 | |
| 131 | static void post_mp_init(void) |
| 132 | { |
| 133 | /* Set Max Ratio */ |
| 134 | cpu_set_max_ratio(); |
| 135 | |
| 136 | /* |
| 137 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 138 | * start flowing. |
| 139 | */ |
Kyösti Mälkki | 040c531 | 2020-05-31 20:03:11 +0300 | [diff] [blame] | 140 | global_smi_enable(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | static const struct mp_ops mp_ops = { |
| 144 | /* |
| 145 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 146 | * that are set prior to ramstage. |
| 147 | * Real MTRRs programming are being done after resource allocation. |
| 148 | */ |
| 149 | .pre_mp_init = soc_fsp_load, |
| 150 | .get_cpu_count = get_cpu_count, |
| 151 | .get_smm_info = smm_info, |
| 152 | .get_microcode_info = get_microcode_info, |
| 153 | .pre_mp_smm_init = smm_initialize, |
| 154 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 155 | .relocation_handler = smm_relocation_handler, |
| 156 | .post_mp_init = post_mp_init, |
| 157 | }; |
| 158 | |
| 159 | void soc_init_cpus(struct bus *cpu_bus) |
| 160 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 161 | /* TODO: Handle mp_init_with_smm failure? */ |
| 162 | mp_init_with_smm(cpu_bus, &mp_ops); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 163 | } |