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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / soc / intel / common / block / spi / spi.c
blob: 914809951ca432fd69f6d131ad9d5f6ba7964828 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]2
3#include <device/device.h>
4#include <device/pci.h>
5#include <device/pci_ids.h>
6#include <device/spi.h>
7#include <intelblocks/fast_spi.h>
8#include <intelblocks/gspi.h>
9#include <intelblocks/spi.h>
10#include <soc/pci_devs.h>
11#include <spi-generic.h>
12
13const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
14 { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]15#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI)
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]16 { .ctrlr = &gspi_ctrlr, .bus_start = 1,
17 .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
18#endif
19};
20
21const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
22
23static int spi_dev_to_bus(struct device *dev)
24{
25 return spi_soc_devfn_to_bus(dev->path.pci.devfn);
26}
27
28static struct spi_bus_operations spi_bus_ops = {
29 .dev_to_bus = &spi_dev_to_bus,
30};
31
32static struct device_operations spi_dev_ops = {
Elyes HAOUAS1d191272018-11-27 12:23:48 +0100[diff] [blame]33 .read_resources = pci_dev_read_resources,
34 .set_resources = pci_dev_set_resources,
35 .enable_resources = pci_dev_enable_resources,
36 .scan_bus = scan_generic_bus,
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]37 .ops_spi_bus = &spi_bus_ops,
Subrata Banik6bbc91a2017-12-07 14:55:51 +0530[diff] [blame]38 .ops_pci = &pci_dev_ops_pci,
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]39};
40
41static const unsigned short pci_device_ids[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]42 PCI_DID_INTEL_SPT_SPI1,
43 PCI_DID_INTEL_SPT_SPI2,
44 PCI_DID_INTEL_SPT_SPI3,
45 PCI_DID_INTEL_APL_SPI0,
46 PCI_DID_INTEL_APL_SPI1,
47 PCI_DID_INTEL_APL_SPI2,
48 PCI_DID_INTEL_APL_HWSEQ_SPI,
49 PCI_DID_INTEL_GLK_SPI0,
50 PCI_DID_INTEL_GLK_SPI1,
51 PCI_DID_INTEL_GLK_SPI2,
52 PCI_DID_INTEL_CNL_SPI0,
53 PCI_DID_INTEL_CNL_SPI1,
54 PCI_DID_INTEL_CNL_SPI2,
55 PCI_DID_INTEL_CNL_HWSEQ_SPI,
56 PCI_DID_INTEL_CNP_H_SPI0,
57 PCI_DID_INTEL_CNP_H_SPI1,
58 PCI_DID_INTEL_CNP_H_SPI2,
59 PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
60 PCI_DID_INTEL_LWB_SPI,
61 PCI_DID_INTEL_LWB_SPI_SUPER,
62 PCI_DID_INTEL_ICP_SPI0,
63 PCI_DID_INTEL_ICP_SPI1,
64 PCI_DID_INTEL_ICP_SPI2,
65 PCI_DID_INTEL_ICP_HWSEQ_SPI,
66 PCI_DID_INTEL_CMP_SPI0,
67 PCI_DID_INTEL_CMP_SPI1,
68 PCI_DID_INTEL_CMP_SPI2,
69 PCI_DID_INTEL_CMP_HWSEQ_SPI,
70 PCI_DID_INTEL_CMP_H_SPI0,
71 PCI_DID_INTEL_CMP_H_SPI1,
72 PCI_DID_INTEL_CMP_H_SPI2,
73 PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
74 PCI_DID_INTEL_TGP_SPI0,
75 PCI_DID_INTEL_TGP_GSPI0,
76 PCI_DID_INTEL_TGP_GSPI1,
77 PCI_DID_INTEL_TGP_GSPI2,
78 PCI_DID_INTEL_TGP_GSPI3,
79 PCI_DID_INTEL_TGP_GSPI4,
80 PCI_DID_INTEL_TGP_GSPI5,
81 PCI_DID_INTEL_TGP_GSPI6,
82 PCI_DID_INTEL_TGP_H_SPI0,
83 PCI_DID_INTEL_TGP_H_GSPI0,
84 PCI_DID_INTEL_TGP_H_GSPI1,
85 PCI_DID_INTEL_TGP_H_GSPI2,
86 PCI_DID_INTEL_TGP_H_GSPI3,
87 PCI_DID_INTEL_MCC_SPI0,
88 PCI_DID_INTEL_MCC_GSPI0,
89 PCI_DID_INTEL_MCC_GSPI1,
90 PCI_DID_INTEL_MCC_GSPI2,
91 PCI_DID_INTEL_JSP_SPI0,
92 PCI_DID_INTEL_JSP_SPI1,
93 PCI_DID_INTEL_JSP_SPI2,
94 PCI_DID_INTEL_JSP_HWSEQ_SPI,
95 PCI_DID_INTEL_ADP_P_HWSEQ_SPI,
96 PCI_DID_INTEL_ADP_S_HWSEQ_SPI,
97 PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI,
98 PCI_DID_INTEL_ADP_P_SPI0,
99 PCI_DID_INTEL_ADP_P_SPI1,
100 PCI_DID_INTEL_ADP_P_SPI2,
101 PCI_DID_INTEL_ADP_P_SPI3,
102 PCI_DID_INTEL_ADP_P_SPI4,
103 PCI_DID_INTEL_ADP_P_SPI5,
104 PCI_DID_INTEL_ADP_P_SPI6,
105 PCI_DID_INTEL_ADP_S_SPI0,
106 PCI_DID_INTEL_ADP_S_SPI1,
107 PCI_DID_INTEL_ADP_S_SPI2,
108 PCI_DID_INTEL_ADP_S_SPI3,
109 PCI_DID_INTEL_ADP_S_SPI4,
110 PCI_DID_INTEL_ADP_S_SPI5,
111 PCI_DID_INTEL_ADP_S_SPI6,
112 PCI_DID_INTEL_ADP_M_N_SPI0,
113 PCI_DID_INTEL_ADP_M_N_SPI1,
114 PCI_DID_INTEL_ADP_M_SPI2,
115 PCI_DID_INTEL_SPR_HWSEQ_SPI,
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]116 0
117};
118
119static const struct pci_driver pch_spi __pci_driver = {
120 .ops = &spi_dev_ops,
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]121 .vendor = PCI_VID_INTEL,
Subrata Banik6c4b5912017-11-07 16:10:05 +0530[diff] [blame]122 .devices = pci_device_ids,
123};