Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <cpu/cpu.h> |
Matt DeVillier | d3d0f07 | 2018-11-10 17:44:36 -0600 | [diff] [blame] | 5 | #include <cpu/intel/common/common.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 6 | #include <cpu/intel/em64t100_save_state.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | #include <cpu/intel/microcode.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 8 | #include <cpu/intel/smm_reloc.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 9 | #include <cpu/intel/turbo.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 10 | #include <cpu/x86/lapic.h> |
| 11 | #include <cpu/x86/mp.h> |
| 12 | #include <cpu/x86/msr.h> |
| 13 | #include <cpu/x86/mtrr.h> |
| 14 | #include <cpu/x86/smm.h> |
Felix Held | e8601f4 | 2021-10-20 23:56:18 +0200 | [diff] [blame] | 15 | #include <device/device.h> |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 16 | #include <reg_script.h> |
Chiranjeevi Rapolu | fd016a4 | 2015-08-11 14:09:46 -0700 | [diff] [blame] | 17 | #include <soc/iosf.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <soc/msr.h> |
| 19 | #include <soc/pattrs.h> |
| 20 | #include <soc/ramstage.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 21 | #include <types.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 23 | /* Core level MSRs */ |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 24 | static const struct reg_script core_msr_script[] = { |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 25 | /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 26 | REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 27 | REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), |
| 28 | |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 29 | /* Disable C1E */ |
| 30 | REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), |
| 31 | REG_MSR_OR(MSR_POWER_MISC, 0x44), |
| 32 | REG_SCRIPT_END |
| 33 | }; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 34 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 35 | static void soc_core_init(struct device *cpu) |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 36 | { |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 37 | printk(BIOS_DEBUG, "Init Braswell core.\n"); |
| 38 | |
| 39 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 40 | * The turbo disable bit is actually scoped at building block level -- not package. |
| 41 | * For non-BSP cores that are within a building block, enable turbo. The cores within |
| 42 | * the BSP's building block will just see it already enabled and move on. |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 43 | */ |
| 44 | if (lapicid()) |
| 45 | enable_turbo(); |
| 46 | |
Matt DeVillier | d3d0f07 | 2018-11-10 17:44:36 -0600 | [diff] [blame] | 47 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 48 | set_vmx_and_lock(); |
Matt DeVillier | d3d0f07 | 2018-11-10 17:44:36 -0600 | [diff] [blame] | 49 | |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 50 | /* Set core MSRs */ |
| 51 | reg_script_run(core_msr_script); |
| 52 | |
| 53 | /* Set this core to max frequency ratio */ |
| 54 | set_max_freq(); |
| 55 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | |
| 57 | static struct device_operations cpu_dev_ops = { |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 58 | .init = soc_core_init, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 61 | static const struct cpu_device_id cpu_table[] = { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 62 | { X86_VENDOR_INTEL, 0x406c4 }, |
| 63 | { X86_VENDOR_INTEL, 0x406c3 }, |
| 64 | { X86_VENDOR_INTEL, 0x406c2 }, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | { 0, 0 }, |
| 66 | }; |
| 67 | |
| 68 | static const struct cpu_driver driver __cpu_driver = { |
| 69 | .ops = &cpu_dev_ops, |
| 70 | .id_table = cpu_table, |
| 71 | }; |
| 72 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 73 | /* |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 74 | * MP and SMM loading initialization. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | */ |
| 76 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 77 | /* Package level MSRs */ |
| 78 | static const struct reg_script package_msr_script[] = { |
| 79 | /* Set Package TDP to ~7W */ |
| 80 | REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), |
| 81 | REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), |
| 82 | REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), |
| 83 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), |
| 84 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), |
| 85 | REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), |
| 86 | REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), |
| 87 | REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), |
| 88 | REG_SCRIPT_END |
| 89 | }; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 90 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 91 | static void pre_mp_init(void) |
| 92 | { |
| 93 | uint32_t bsmrwac; |
| 94 | |
| 95 | /* Set up MTRRs based on physical address size. */ |
| 96 | x86_setup_mtrrs_with_detect(); |
| 97 | x86_mtrr_check(); |
| 98 | |
| 99 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 100 | * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines |
| 101 | * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped. |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 102 | */ |
| 103 | bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; |
| 104 | iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); |
| 105 | |
| 106 | /* Set package MSRs */ |
| 107 | reg_script_run(package_msr_script); |
| 108 | |
| 109 | /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ |
| 110 | enable_turbo(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 111 | } |
| 112 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 113 | static int get_cpu_count(void) |
| 114 | { |
| 115 | const struct pattrs *pattrs = pattrs_get(); |
| 116 | |
| 117 | return pattrs->num_cpus; |
| 118 | } |
| 119 | |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 120 | static void fill_in_relocation_params(struct smm_relocation_params *params) |
| 121 | { |
| 122 | uintptr_t tseg_base; |
| 123 | size_t tseg_size; |
| 124 | |
| 125 | /* All range registers are aligned to 4KiB */ |
| 126 | const u32 rmask = ~((1 << 12) - 1); |
| 127 | |
| 128 | smm_region(&tseg_base, &tseg_size); |
| 129 | |
| 130 | /* SMRR has 32-bits of valid address aligned to 4KiB. */ |
| 131 | params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; |
| 132 | params->smrr_base.hi = 0; |
| 133 | params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; |
| 134 | params->smrr_mask.hi = 0; |
| 135 | } |
| 136 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 137 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 138 | size_t *smm_save_state_size) |
| 139 | { |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 140 | printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 141 | |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 142 | fill_in_relocation_params(&smm_reloc_params); |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 143 | |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 144 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 145 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 146 | *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 147 | } |
| 148 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 149 | static void get_microcode_info(const void **microcode, int *parallel) |
| 150 | { |
| 151 | const struct pattrs *pattrs = pattrs_get(); |
| 152 | |
| 153 | *microcode = pattrs->microcode_patch; |
Patrick Rudolph | ce51b34 | 2021-01-11 09:21:58 +0100 | [diff] [blame] | 154 | *parallel = !intel_ht_supported(); |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static void per_cpu_smm_trigger(void) |
| 158 | { |
| 159 | const struct pattrs *pattrs = pattrs_get(); |
| 160 | msr_t msr_value; |
| 161 | |
| 162 | /* Need to make sure that all cores have microcode loaded. */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 163 | msr_value = rdmsr(IA32_BIOS_SIGN_ID); |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 164 | if (msr_value.hi == 0) |
| 165 | intel_microcode_load_unlocked(pattrs->microcode_patch); |
| 166 | |
| 167 | /* Relocate SMM space. */ |
| 168 | smm_initiate_relocation(); |
| 169 | |
| 170 | /* Load microcode after SMM relocation. */ |
| 171 | intel_microcode_load_unlocked(pattrs->microcode_patch); |
| 172 | } |
| 173 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 174 | static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 175 | { |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 176 | struct smm_relocation_params *relo_params = &smm_reloc_params; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 177 | em64t100_smm_state_save_area_t *smm_state; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 178 | |
| 179 | /* Set up SMRR. */ |
Kyösti Mälkki | b371e23 | 2019-08-06 06:32:46 +0300 | [diff] [blame] | 180 | wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); |
| 181 | wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 182 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 183 | smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); |
| 184 | smm_state->smbase = staggered_smbase; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 187 | static void post_mp_init(void) |
| 188 | { |
| 189 | global_smi_enable(); |
| 190 | } |
| 191 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 192 | static const struct mp_ops mp_ops = { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 193 | .pre_mp_init = pre_mp_init, |
| 194 | .get_cpu_count = get_cpu_count, |
| 195 | .get_smm_info = get_smm_info, |
| 196 | .get_microcode_info = get_microcode_info, |
| 197 | .pre_mp_smm_init = smm_southbridge_clear_state, |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 198 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 199 | .relocation_handler = relocation_handler, |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 200 | .post_mp_init = post_mp_init, |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 201 | }; |
| 202 | |
Felix Held | e8601f4 | 2021-10-20 23:56:18 +0200 | [diff] [blame] | 203 | void mp_init_cpus(struct bus *cpu_bus) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 204 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 205 | /* TODO: Handle mp_init_with_smm failure? */ |
| 206 | mp_init_with_smm(cpu_bus, &mp_ops); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 207 | } |