| Felix Held | 38712b8 | 2022-01-04 21:02:00 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef AMD_BLOCK_ESPI_DEF_H |
| 4 | #define AMD_BLOCK_ESPI_DEF_H |
| 5 | |
| 6 | #define ESPI_DN_TX_HDR0 0x00 |
| 7 | #define ESPI_DN_TX_HDR1 0x04 |
| 8 | #define ESPI_DN_TX_HDR2 0x08 |
| 9 | #define ESPI_DN_TX_DATA 0x0c |
| 10 | |
| 11 | #define ESPI_MASTER_CAP 0x2c |
| 12 | #define ESPI_VW_MAX_SIZE_SHIFT 13 |
| 13 | #define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) |
| 14 | |
| 15 | #define ESPI_GLOBAL_CONTROL_0 0x30 |
| 16 | #define ESPI_WAIT_CNT_SHIFT 24 |
| 17 | #define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) |
| 18 | #define ESPI_WDG_CNT_SHIFT 8 |
| 19 | #define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) |
| 20 | #define ESPI_AL_IDLE_TIMER_SHIFT 4 |
| 21 | #define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) |
| 22 | #define ESPI_AL_STOP_EN (1 << 3) |
| 23 | #define ESPI_PR_CLKGAT_EN (1 << 2) |
| 24 | #define ESPI_WAIT_CHKEN (1 << 1) |
| 25 | #define ESPI_WDG_EN (1 << 0) |
| 26 | |
| 27 | #define ESPI_GLOBAL_CONTROL_1 0x34 |
| 28 | #define ESPI_RGCMD_INT_MAP_SHIFT 13 |
| 29 | #define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) |
| 30 | #define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) |
| 31 | #define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) |
| 32 | #define ESPI_ERR_INT_MAP_SHIFT 8 |
| 33 | #define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) |
| 34 | #define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) |
| 35 | #define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) |
| 36 | #define ESPI_SUB_DECODE_SLV_SHIFT 3 |
| 37 | #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) |
| 38 | #define ESPI_SUB_DECODE_EN (1 << 2) |
| 39 | #define ESPI_BUS_MASTER_EN (1 << 1) |
| 40 | #define ESPI_SW_RST (1 << 0) |
| 41 | |
| 42 | #define ESPI_SLAVE0_INT_EN 0x6c |
| 43 | #define ESPI_SLAVE0_INT_STS 0x70 |
| 44 | #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) |
| 45 | #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) |
| 46 | #define ESPI_STATUS_FATAL_ERROR (1 << 5) |
| 47 | #define ESPI_STATUS_NO_RESPONSE (1 << 4) |
| 48 | #define ESPI_STATUS_CRC_ERR (1 << 2) |
| 49 | #define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) |
| 50 | #define ESPI_STATUS_BUS_ERROR (1 << 0) |
| 51 | |
| 52 | #define ESPI_RXVW_POLARITY 0xac |
| 53 | |
| 54 | #endif /* AMD_BLOCK_ESPI_DEF_H */ |