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Mario Scheithauer5716b4c2018-11-14 13:27:05 +01001chip soc/intel/apollolake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
7 register "sci_irq" = "SCIS_IRQ10"
8
Mario Scheithauer5716b4c2018-11-14 13:27:05 +01009 # EMMC TX DATA Delay 1
10 # Refer to EDS-Vol2-22.3.
11 # [14:8] steps of delay for HS400, each 125ps.
12 # [6:0] steps of delay for SDR104/HS200, each 125ps.
13 register "emmc_tx_data_cntl1" = "0x0C16"
14
15 # EMMC TX DATA Delay 2
16 # Refer to EDS-Vol2-22.3.
17 # [30:24] steps of delay for SDR50, each 125ps.
18 # [22:16] steps of delay for DDR50, each 125ps.
19 # [14:8] steps of delay for SDR25/HS50, each 125ps.
20 # [6:0] steps of delay for SDR12, each 125ps.
21 register "emmc_tx_data_cntl2" = "0x28162828"
22
23 # EMMC RX CMD/DATA Delay 1
24 # Refer to EDS-Vol2-22.3.
25 # [30:24] steps of delay for SDR50, each 125ps.
26 # [22:16] steps of delay for DDR50, each 125ps.
27 # [14:8] steps of delay for SDR25/HS50, each 125ps.
28 # [6:0] steps of delay for SDR12, each 125ps.
29 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
30
31 # EMMC RX CMD/DATA Delay 2
32 # Refer to EDS-Vol2-22.3.
33 # [17:16] stands for Rx Clock before Output Buffer
34 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
35 # [6:0] steps of delay for HS200, each 125ps.
36 register "emmc_rx_cmd_data_cntl2" = "0x10008"
37
38 # 0:HS400(Default), 1:HS200, 2:DDR50
Mario Scheithauer1f21a962019-07-10 13:15:54 +020039 register "emmc_host_max_speed" = "1"
Mario Scheithauer5716b4c2018-11-14 13:27:05 +010040
Werner Zehd7e5f4b2019-02-01 12:39:40 +010041 # Enable Vtd feature
42 register "enable_vtd" = "1"
43
Werner Zeh45f44942021-04-27 11:40:17 +020044 # I2C0 controller used for RTC
45 register "common_soc_config" = "{
46 .i2c[0] = {
47 .speed = I2C_SPEED_STANDARD,
48 .rise_time_ns = 160,
49 .fall_time_ns = 110,
Werner Zeha67bda32021-05-31 07:15:36 +020050 .data_hold_time_ns = 300,
51 .speed_config[0] = {
52 .speed = I2C_SPEED_FAST,
53 .scl_hcnt = 0x5b,
54 .scl_lcnt = 0xce,
55 .sda_hold = 0x28
56 },
Werner Zeh45f44942021-04-27 11:40:17 +020057 },
58 }"
59
Mario Scheithauer5716b4c2018-11-14 13:27:05 +010060 device domain 0 on
61 device pci 00.0 on end # - Host Bridge
62 device pci 00.1 off end # - DPTF
63 device pci 00.2 off end # - NPK
64 device pci 02.0 on end # - Gen - Display
65 device pci 03.0 off end # - Iunit
66 device pci 0d.0 on end # - P2SB
67 device pci 0d.1 off end # - PMC
68 device pci 0d.2 on end # - SPI
69 device pci 0d.3 off end # - Shared SRAM
Werner Zeha4e52362019-04-12 09:10:27 +020070 device pci 0e.0 on end # - Audio
Subrata Banike9b93732020-09-17 15:48:54 +053071 device pci 0f.0 on end # - CSE
Mario Scheithauer5716b4c2018-11-14 13:27:05 +010072 device pci 11.0 on end # - ISH
Mario Scheithauerf0232702022-01-26 11:53:00 +010073 device pci 12.0 on # - SATA
74 register "DisableSataSalpSupport" = "1"
75 end
Mario Scheithauer92e4ed12021-01-14 14:54:38 +010076 device pci 13.0 on # - RP 2 - PCIe A 0
77 register "pcie_rp_clkreq_pin[2]" = "0"
78 register "pcie_rp_hotplug_enable[2]" = "0"
79 end
80 device pci 13.1 off # - RP 3 - PCIe A 1
81 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
82 end
83 device pci 13.2 on # - RP 4 - PCIe-A 2
84 register "pcie_rp_clkreq_pin[4]" = "2"
85 register "pcie_rp_hotplug_enable[4]" = "0"
86 end
87 device pci 13.3 on # - RP 5 - PCIe-A 3
88 register "pcie_rp_clkreq_pin[5]" = "3"
89 register "pcie_rp_hotplug_enable[5]" = "0"
90 end
91 device pci 14.0 on # - RP 0 - PCIe-B 0
92 register "pcie_rp_clkreq_pin[0]" = "1"
93 register "pcie_rp_hotplug_enable[0]" = "0"
94 end
95 device pci 14.1 off # - RP 1 - PCIe-B 1
96 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
97 end
Mario Scheithauer5716b4c2018-11-14 13:27:05 +010098 device pci 15.0 on end # - XHCI
99 device pci 15.1 off end # - XDCI
100 device pci 16.0 on # - I2C 0
101 # Enable external RTC chip
102 chip drivers/i2c/rx6110sa
103 register "pmon_sampling" = "PMON_SAMPL_256_MS"
104 register "bks_on" = "0"
105 register "bks_off" = "1"
106 register "iocut_en" = "1"
107 register "set_user_date" = "1"
108 register "user_year" = "04"
109 register "user_month" = "07"
110 register "user_day" = "01"
111 register "user_weekday" = "4"
112 device i2c 0x32 on end # RTC RX6110 SA
113 end
Uwe Poeche99658852019-11-05 15:44:42 +0100114 # Enable external display bridge (eDP to LVDS)
115 chip drivers/i2c/ptn3460
116 device i2c 0x20 on end # PTN3460 DP2LVDS Bridge
117 end
Mario Scheithauer5716b4c2018-11-14 13:27:05 +0100118 end
119 device pci 16.1 off end # - I2C 1
120 device pci 16.2 off end # - I2C 2
121 device pci 16.3 off end # - I2C 3
122 device pci 17.0 off end # - I2C 4
123 device pci 17.1 off end # - I2C 5
124 device pci 17.2 off end # - I2C 6
125 device pci 17.3 on end # - I2C 7
126 device pci 18.0 on end # - UART 0
127 device pci 18.1 on end # - UART 1
128 device pci 18.2 on end # - UART 2
129 device pci 18.3 on end # - UART 3
130 device pci 19.0 off end # - SPI 0
131 device pci 19.1 off end # - SPI 1
132 device pci 19.2 off end # - SPI 2
133 device pci 1a.0 off end # - PWM
Mario Scheithauer36a4a9d2018-11-28 08:37:31 +0100134 device pci 1b.0 on end # - SDCARD
Mario Scheithauer5716b4c2018-11-14 13:27:05 +0100135 device pci 1c.0 on end # - eMMC
136 device pci 1d.0 off end # - UFS
137 device pci 1e.0 off end # - SDIO
Elyes HAOUASbda27cd2020-06-27 07:17:16 +0200138 device pci 1f.0 on # - LPC
Mario Scheithauer37fedc02019-06-03 16:35:25 +0200139 chip drivers/pc80/tpm
140 device pnp 0c31.0 on end
141 end
142 end
Mario Scheithauer5716b4c2018-11-14 13:27:05 +0100143 device pci 1f.1 on end # - SMBUS
144 end
145end