blob: 6c17d6329870be8b75e95f164e7892db7aaa9e53 [file] [log] [blame]
Mario Scheithauer66038c82018-09-25 17:26:32 +02001chip soc/intel/apollolake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
7 register "sci_irq" = "SCIS_IRQ10"
Mario Scheithauer66038c82018-09-25 17:26:32 +02008
Mario Scheithauer66038c82018-09-25 17:26:32 +02009 # EMMC TX DATA Delay 1
10 # Refer to EDS-Vol2-22.3.
11 # [14:8] steps of delay for HS400, each 125ps.
12 # [6:0] steps of delay for SDR104/HS200, each 125ps.
13 register "emmc_tx_data_cntl1" = "0x0C16"
14
15 # EMMC TX DATA Delay 2
16 # Refer to EDS-Vol2-22.3.
17 # [30:24] steps of delay for SDR50, each 125ps.
18 # [22:16] steps of delay for DDR50, each 125ps.
19 # [14:8] steps of delay for SDR25/HS50, each 125ps.
20 # [6:0] steps of delay for SDR12, each 125ps.
21 register "emmc_tx_data_cntl2" = "0x28162828"
22
23 # EMMC RX CMD/DATA Delay 1
24 # Refer to EDS-Vol2-22.3.
25 # [30:24] steps of delay for SDR50, each 125ps.
26 # [22:16] steps of delay for DDR50, each 125ps.
27 # [14:8] steps of delay for SDR25/HS50, each 125ps.
28 # [6:0] steps of delay for SDR12, each 125ps.
29 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
30
31 # EMMC RX CMD/DATA Delay 2
32 # Refer to EDS-Vol2-22.3.
33 # [17:16] stands for Rx Clock before Output Buffer
34 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
35 # [6:0] steps of delay for HS200, each 125ps.
36 register "emmc_rx_cmd_data_cntl2" = "0x10008"
37
38 # 0:HS400(Default), 1:HS200, 2:DDR50
Mario Scheithauer1f21a962019-07-10 13:15:54 +020039 register "emmc_host_max_speed" = "1"
Mario Scheithauer66038c82018-09-25 17:26:32 +020040
Werner Zehd7e5f4b2019-02-01 12:39:40 +010041 # Enable Vtd feature
42 register "enable_vtd" = "1"
43
Werner Zeh45f44942021-04-27 11:40:17 +020044 # I2C3 controller used for RTC
45 register "common_soc_config" = "{
46 .i2c[3] = {
47 .speed = I2C_SPEED_STANDARD,
48 .rise_time_ns = 60,
49 .fall_time_ns = 20,
Werner Zeha67bda32021-05-31 07:15:36 +020050 .data_hold_time_ns = 300,
51 .speed_config[0] = {
52 .speed = I2C_SPEED_FAST,
53 .scl_hcnt = 0x68,
54 .scl_lcnt = 0xd4,
55 .sda_hold = 0x28
56 },
Werner Zeh45f44942021-04-27 11:40:17 +020057 },
58 }"
59
Mario Scheithauer66038c82018-09-25 17:26:32 +020060 device domain 0 on
61 device pci 00.0 on end # - Host Bridge
62 device pci 00.1 off end # - DPTF
63 device pci 00.2 off end # - NPK
64 device pci 02.0 on end # - Gen - Display
65 device pci 03.0 off end # - Iunit
66 device pci 0d.0 on end # - P2SB
67 device pci 0d.1 off end # - PMC
68 device pci 0d.2 on end # - SPI
69 device pci 0d.3 off end # - Shared SRAM
Werner Zeha4e52362019-04-12 09:10:27 +020070 device pci 0e.0 on end # - Audio
Subrata Banike9b93732020-09-17 15:48:54 +053071 device pci 0f.0 on end # - CSE
Mario Scheithauer66038c82018-09-25 17:26:32 +020072 device pci 11.0 on end # - ISH
Mario Scheithauerf0232702022-01-26 11:53:00 +010073 device pci 12.0 on # - SATA
74 register "DisableSataSalpSupport" = "1"
75 end
Mario Scheithauer92e4ed12021-01-14 14:54:38 +010076 device pci 13.0 on # - RP 2 - PCIe A 0
77 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
78 register "pcie_rp_hotplug_enable[2]" = "0"
79 end
80 device pci 13.1 on # - RP 3 - PCIe A 1
81 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
82 register "pcie_rp_hotplug_enable[3]" = "0"
83 end
84 device pci 13.2 on # - RP 4 - PCIe-A 2
85 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
86 register "pcie_rp_hotplug_enable[4]" = "0"
87 end
88 device pci 13.3 on # - RP 5 - PCIe-A 3
89 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
90 register "pcie_rp_hotplug_enable[5]" = "0"
91 end
92 device pci 14.0 on # - RP 0 - PCIe-B 0
93 register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
94 register "pcie_rp_hotplug_enable[0]" = "0"
95 end
96 device pci 14.1 on # - RP 1 - PCIe-B 1
97 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
98 register "pcie_rp_hotplug_enable[1]" = "0"
99 end
Mario Scheithauer66038c82018-09-25 17:26:32 +0200100 device pci 15.0 on end # - XHCI
101 device pci 15.1 off end # - XDCI
Werner Zeh6f74d382022-02-21 07:52:13 +0100102 device pci 16.0 on end # - I2C 0
Werner Zehb2bb9592021-05-31 07:27:50 +0200103 device pci 16.1 off end # - I2C 1
104 device pci 16.2 off end # - I2C 2
Mario Scheithauer1cd95b02021-02-08 13:45:26 +0100105 device pci 16.3 on # - I2C 3
Mario Scheithauer66038c82018-09-25 17:26:32 +0200106 # Enable external RTC chip
107 chip drivers/i2c/rx6110sa
108 register "pmon_sampling" = "PMON_SAMPL_256_MS"
109 register "bks_on" = "0"
110 register "bks_off" = "1"
111 register "iocut_en" = "1"
112 register "set_user_date" = "1"
113 register "user_year" = "04"
114 register "user_month" = "07"
115 register "user_day" = "01"
116 register "user_weekday" = "4"
117 device i2c 0x32 on end # RTC RX6110 SA
118 end
119 end
Werner Zehb2bb9592021-05-31 07:27:50 +0200120 device pci 17.0 off end # - I2C 4
121 device pci 17.1 off end # - I2C 5
122 device pci 17.2 off end # - I2C 6
123 device pci 17.3 off end # - I2C 7
Mario Scheithauerddf84982019-01-29 08:38:54 +0100124 device pci 18.0 on end # - UART 0
125 device pci 18.1 on end # - UART 1
126 device pci 18.2 on end # - UART 2
127 device pci 18.3 on end # - UART 3
Mario Scheithauer66038c82018-09-25 17:26:32 +0200128 device pci 19.0 off end # - SPI 0
129 device pci 19.1 off end # - SPI 1
130 device pci 19.2 off end # - SPI 2
131 device pci 1a.0 off end # - PWM
132 device pci 1b.0 on end # - SDCARD
133 device pci 1c.0 on end # - eMMC
134 device pci 1d.0 off end # - UFS
135 device pci 1e.0 off end # - SDIO
Mario Scheithauer67be4912019-01-28 16:18:45 +0100136 device pci 1f.0 on # - LPC
137 chip drivers/pc80/tpm
138 device pnp 0c31.0 on end
139 end
140 end
Mario Scheithauer66038c82018-09-25 17:26:32 +0200141 device pci 1f.1 on end # - SMBUS
142 end
143end