| Thomas Heijligen | ca9eb1a | 2019-03-19 12:12:46 +0100 | [diff] [blame] | 1 | comment "MC APLx" |
| 2 | |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 3 | config BOARD_SIEMENS_MC_APL1 |
| Mario Scheithauer | 66038c8 | 2018-09-25 17:26:32 +0200 | [diff] [blame] | 4 | bool "-> MC APL1" |
| 5 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| 6 | |
| 7 | config BOARD_SIEMENS_MC_APL2 |
| 8 | bool "-> MC APL2" |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 9 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 10 | |
| 11 | config BOARD_SIEMENS_MC_APL3 |
| 12 | bool "-> MC APL3" |
| 13 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 14 | |
| 15 | config BOARD_SIEMENS_MC_APL4 |
| 16 | bool "-> MC APL4" |
| 17 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| Werner Zeh | f57b05b | 2019-09-24 09:48:19 +0200 | [diff] [blame] | 18 | |
| 19 | config BOARD_SIEMENS_MC_APL5 |
| 20 | bool "-> MC APL5" |
| 21 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 22 | |
| 23 | config BOARD_SIEMENS_MC_APL6 |
| 24 | bool "-> MC APL6" |
| 25 | select BOARD_SIEMENS_BASEBOARD_MC_APL1 |