| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 1 | |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 2 | config BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| 3 | def_bool n |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 4 | select SOC_INTEL_APOLLOLAKE |
| 5 | select BOARD_ROMSIZE_KB_16384 |
| 6 | select HAVE_ACPI_TABLES |
| Mario Scheithauer | 480eab0 | 2017-02-16 13:39:16 +0100 | [diff] [blame] | 7 | select USE_SIEMENS_HWILIB |
| Mario Scheithauer | dd21736 | 2019-01-11 14:25:38 +0100 | [diff] [blame] | 8 | select INTEL_LPSS_UART_FOR_CONSOLE |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 9 | |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 10 | source "src/mainboard/siemens/mc_apl1/variants/*/Kconfig" |
| 11 | |
| 12 | if BOARD_SIEMENS_BASEBOARD_MC_APL1 |
| 13 | |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 14 | config MAINBOARD_DIR |
| Patrick Georgi | 0bb8346 | 2019-11-22 20:58:58 +0100 | [diff] [blame] | 15 | default "siemens/mc_apl1" |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 16 | |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 17 | config VARIANT_DIR |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 18 | default "mc_apl1" if BOARD_SIEMENS_MC_APL1 |
| Mario Scheithauer | 66038c8 | 2018-09-25 17:26:32 +0200 | [diff] [blame] | 19 | default "mc_apl2" if BOARD_SIEMENS_MC_APL2 |
| Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 20 | default "mc_apl3" if BOARD_SIEMENS_MC_APL3 |
| Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 21 | default "mc_apl4" if BOARD_SIEMENS_MC_APL4 |
| Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 22 | default "mc_apl5" if BOARD_SIEMENS_MC_APL5 |
| Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 23 | default "mc_apl6" if BOARD_SIEMENS_MC_APL6 |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 24 | |
| Peter Lemenkov | 395cbb4 | 2018-11-06 22:09:18 +0100 | [diff] [blame] | 25 | config DEVICETREE |
| Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 26 | default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" |
| Peter Lemenkov | 395cbb4 | 2018-11-06 22:09:18 +0100 | [diff] [blame] | 27 | |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 28 | config MAINBOARD_PART_NUMBER |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 29 | default "MC APL1" if BOARD_SIEMENS_MC_APL1 |
| Mario Scheithauer | 66038c8 | 2018-09-25 17:26:32 +0200 | [diff] [blame] | 30 | default "MC APL2" if BOARD_SIEMENS_MC_APL2 |
| Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 31 | default "MC APL3" if BOARD_SIEMENS_MC_APL3 |
| Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 32 | default "MC APL4" if BOARD_SIEMENS_MC_APL4 |
| Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 33 | default "MC APL5" if BOARD_SIEMENS_MC_APL5 |
| Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 34 | default "MC APL6" if BOARD_SIEMENS_MC_APL6 |
| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 35 | |
| Mario Scheithauer | dd21736 | 2019-01-11 14:25:38 +0100 | [diff] [blame] | 36 | config UART_FOR_CONSOLE |
| 37 | default 2 |
| 38 | |
| Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 39 | endif # BOARD_SIEMENS_BASEBOARD_MC_APL1 |