Usha P | 112fde0 | 2021-12-07 06:56:42 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
| 6 | |
| 7 | /* Pad configuration in ramstage*/ |
| 8 | static const struct pad_config gpio_table[] = { |
| 9 | /* ESPI_IO0_EC_R / ESPI_IO0_HDR */ |
| 10 | PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), |
| 11 | /* ESPI_IO1_EC_R / ESPI_IO1_HDR */ |
| 12 | PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), |
| 13 | /* ESPI_IO2_EC_R / ESPI_IO2_HDR */ |
| 14 | PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), |
| 15 | /* ESPI_IO3_EC_R / ESPI_IO3_HDR */ |
| 16 | PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), |
| 17 | /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */ |
| 18 | PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), |
| 19 | /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */ |
| 20 | PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), |
| 21 | /* ESPI_CLK_EC_R / ESPI_CLK_HDR */ |
| 22 | PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), |
| 23 | /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */ |
| 24 | PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), |
| 25 | |
| 26 | /* EC_SLP_S0_CS_N */ |
| 27 | PAD_CFG_GPO(GPP_E4, 1, PLTRST), |
| 28 | |
Usha P | 112fde0 | 2021-12-07 06:56:42 +0530 | [diff] [blame] | 29 | /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ |
| 30 | PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), |
| 31 | /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ |
| 32 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 33 | |
| 34 | /* M.2_SSD_PDET_R */ |
| 35 | PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), |
| 36 | /* CLKREQ0_M2_SSD_N */ |
| 37 | PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |
| 38 | /* M2_PCH_SSD_PWREN */ |
| 39 | PAD_CFG_GPO(GPP_D16, 1, PLTRST), |
| 40 | /* M2_SSD_RST_N */ |
| 41 | PAD_CFG_GPO(GPP_H0, 1, PLTRST), |
| 42 | /* M2_SSD_DEVSLP */ |
| 43 | PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), |
| 44 | |
Krishna Prasad Bhat | e1ff978 | 2022-01-16 23:19:52 +0530 | [diff] [blame] | 45 | /* I5 : NC */ |
| 46 | PAD_NC(GPP_I5, NONE), |
| 47 | /* I7 : EMMC_CMD ==> EMMC_CMD */ |
| 48 | PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), |
| 49 | /* I8 : EMMC_DATA0 ==> EMMC_D0 */ |
| 50 | PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), |
| 51 | /* I9 : EMMC_DATA1 ==> EMMC_D1 */ |
| 52 | PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), |
| 53 | /* I10 : EMMC_DATA2 ==> EMMC_D2 */ |
| 54 | PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), |
| 55 | /* I11 : EMMC_DATA3 ==> EMMC_D3 */ |
| 56 | PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), |
| 57 | /* I12 : EMMC_DATA4 ==> EMMC_D4 */ |
| 58 | PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), |
| 59 | /* I13 : EMMC_DATA5 ==> EMMC_D5 */ |
| 60 | PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), |
| 61 | /* I14 : EMMC_DATA6 ==> EMMC_D6 */ |
| 62 | PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), |
| 63 | /* I15 : EMMC_DATA7 ==> EMMC_D7 */ |
| 64 | PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), |
| 65 | /* I16 : EMMC_RCLK ==> EMMC_RCLK */ |
| 66 | PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), |
| 67 | /* I17 : EMMC_CLK ==> EMMC_CLK */ |
| 68 | PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), |
| 69 | /* I18 : EMMC_RESET# ==> EMMC_RST_L */ |
| 70 | PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), |
| 71 | |
Usha P | 112fde0 | 2021-12-07 06:56:42 +0530 | [diff] [blame] | 72 | /* TYPEA_CONN23_USB2_P8_OC1_N */ |
| 73 | PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), |
| 74 | /* CRD1_PWREN */ |
| 75 | PAD_CFG_GPO(GPP_B23, 1, PLTRST), |
| 76 | /* TCP1_DISP_AUX_P_BIAS_GPIO */ |
| 77 | PAD_CFG_GPO(GPP_E20, 1, PLTRST), |
| 78 | /* TCP1_DISP_AUX_N_BIAS_GPIO */ |
| 79 | PAD_CFG_GPO(GPP_E21, 0, PLTRST), |
| 80 | /* TCP0_DISP_AUX_P_BIAS_GPIO */ |
| 81 | PAD_CFG_GPO(GPP_E22, 0, PLTRST), |
| 82 | /* TCP0_DISP_AUX_N_BIAS_GPIO */ |
| 83 | PAD_CFG_GPO(GPP_E23, 1, PLTRST), |
| 84 | |
| 85 | /* EDP1_HPD_MIPI_PNL_RST */ |
| 86 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 87 | |
| 88 | /* X1_SLOT_PWREN */ |
| 89 | PAD_CFG_GPO(GPP_A8, 0, PLTRST), |
| 90 | /* SML0_CLK */ |
| 91 | PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), |
| 92 | /* SML0_DATA */ |
| 93 | PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), |
| 94 | /* CLKREQ3_X1PCIE_SLOT_N */ |
| 95 | PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 96 | /* X1_PCIE_SLOT_WAKE_N */ |
| 97 | PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT), |
| 98 | /* X1_Slot_RESET */ |
| 99 | PAD_CFG_GPO(GPP_F10, 1, PLTRST), |
| 100 | |
| 101 | /* WWAN_PERST_N */ |
| 102 | PAD_CFG_GPO(GPP_C5, 1, PLTRST), |
| 103 | /* CLKREQ1_WWAN_N */ |
| 104 | PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), |
| 105 | /* GPPC_D15_M.2_WWAN_DISABLE_N */ |
| 106 | PAD_CFG_GPO(GPP_D15, 1, PLTRST), |
| 107 | /* WWAN_PWREN */ |
| 108 | PAD_CFG_GPO(GPP_D17, 1, PLTRST), |
| 109 | /* WWAN WAKE N */ |
| 110 | PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI |
| 111 | /* SRCCLK_OEB6 */ |
| 112 | PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3), |
| 113 | /* GPPC_F6_CNV_PA_BLANKING */ |
| 114 | PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), |
| 115 | /* WWAN_RST# */ |
| 116 | PAD_CFG_GPO(GPP_F14, 1, PLTRST), |
| 117 | /* WWAN_FCP_OFF_N */ |
| 118 | PAD_CFG_GPO(GPP_F15, 1, PLTRST), |
| 119 | /* CNV_MFUART2_RXD */ |
| 120 | PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), |
| 121 | /* CNV_MFUART2_RXD */ |
| 122 | PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), |
| 123 | |
| 124 | /* PM_SLP_S0_N */ |
| 125 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 126 | /* PLT_RST_N */ |
| 127 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 128 | /* PM_SLP_DRAM_N */ |
| 129 | PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), |
| 130 | /* CPU_C10_GATE_N_R */ |
| 131 | PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), |
| 132 | |
| 133 | /* CODEC_INT_N */ |
| 134 | PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), |
| 135 | /* SNDW0_CLK_HDR */ |
| 136 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), |
| 137 | /* SNDW0_DATA_HDR */ |
| 138 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), |
| 139 | /* SNDW1_CLK_DMIC_CLK_A_0 */ |
| 140 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), |
| 141 | /* SNDW1_DATA_DMIC_DATA_0 */ |
| 142 | PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), |
| 143 | /* SNDW2_CLK_R */ |
| 144 | PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), |
| 145 | /* SNDW2_DATA_R */ |
| 146 | PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), |
| 147 | /* SOC_DMIC0_SNDW3_CLK */ |
| 148 | PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), |
| 149 | /* SOC_DMIC0_SNDW3_DATA */ |
| 150 | PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), |
| 151 | |
| 152 | /* I2C_SCL(0) */ |
| 153 | PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), |
| 154 | /* I2C_SDA(0) */ |
| 155 | PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), |
| 156 | |
| 157 | /* DDIB_DP_HDMI_ALS_HDP */ |
| 158 | PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 159 | |
| 160 | /* 8 : M.2_BTWIFI_SUS_CLK */ |
| 161 | PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 162 | /* 9 : GPD_9_SLP_WLAN_N */ |
| 163 | PAD_CFG_NF(GPD9, NONE, DEEP, NF1), |
| 164 | |
| 165 | /* SRCCLK_OEB7 */ |
| 166 | PAD_CFG_GPO(GPP_A7, 0, PLTRST), |
| 167 | |
| 168 | /* GPIO pin for PCIE SRCCLKREQB_2 */ |
| 169 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 170 | |
| 171 | /* H2 : WLAN_RST_N */ |
| 172 | PAD_CFG_GPO(GPP_H2, 1, PLTRST), |
| 173 | /* I2C_SDA(1) */ |
| 174 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 175 | /* I2C_SCL(1) */ |
| 176 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 177 | |
| 178 | /* CAM_PRIVACY_LED */ |
| 179 | PAD_CFG_GPO(GPP_B14, 1, PLTRST), |
| 180 | |
| 181 | /* B16 : I2C5 SDA */ |
| 182 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), |
| 183 | /* B17 : I2C5 SCL */ |
| 184 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), |
| 185 | |
| 186 | /* CAM_STROBE */ |
| 187 | PAD_CFG_GPO(GPP_B18, 0, PLTRST), |
Usha P | 36871db | 2022-01-17 21:36:27 +0530 | [diff] [blame] | 188 | /* CAM1_RST_N */ |
| 189 | PAD_CFG_GPO(GPP_A21, 1, PLTRST), |
Usha P | 112fde0 | 2021-12-07 06:56:42 +0530 | [diff] [blame] | 190 | /* CAM1_PWR_EN */ |
| 191 | PAD_CFG_GPO(GPP_B23, 1, PLTRST), |
| 192 | /* CAM2_RST */ |
| 193 | PAD_CFG_GPO(GPP_E15, 1, PLTRST), |
| 194 | /* CAM2_PWR_EN */ |
| 195 | PAD_CFG_GPO(GPP_E16, 1, PLTRST), |
| 196 | |
| 197 | /* IMGCLKOUT */ |
| 198 | PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), |
| 199 | PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), |
| 200 | PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), |
| 201 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 202 | |
| 203 | /* BT_RF_KILL_N */ |
| 204 | PAD_CFG_GPO(GPP_A13, 1, PLTRST), |
| 205 | |
| 206 | /* D13 : WIFI_WAKE_N */ |
| 207 | PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), |
| 208 | /* WIFI RF KILL */ |
| 209 | PAD_CFG_GPO(GPP_E3, 1, PLTRST), |
| 210 | |
| 211 | /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ |
| 212 | PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), |
| 213 | /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ |
| 214 | PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), |
| 215 | /* F2 : CNV_RGI_DT_BT_UART2_TXD */ |
| 216 | PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), |
| 217 | /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ |
| 218 | PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), |
| 219 | /* F4 : CNV_RF_RESET_R_N */ |
| 220 | PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), |
| 221 | /* F5 : MODEM_CLKREQ_R */ |
| 222 | PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), |
| 223 | /* TCH PAD Power EN */ |
| 224 | PAD_CFG_GPO(GPP_F7, 1, PLTRST), |
| 225 | |
| 226 | /* UART_BT_WAKE_N */ |
| 227 | PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), |
| 228 | }; |
| 229 | |
| 230 | void variant_configure_gpio_pads(void) |
| 231 | { |
| 232 | gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); |
| 233 | } |
| 234 | |
| 235 | static const struct cros_gpio cros_gpios[] = { |
| 236 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 237 | }; |
| 238 | |
| 239 | const struct cros_gpio *variant_cros_gpios(size_t *num) |
| 240 | { |
| 241 | *num = ARRAY_SIZE(cros_gpios); |
| 242 | return cros_gpios; |
| 243 | } |