Angel Pons | b6636b0 | 2020-04-05 13:21:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 2 | |
Aamir Bohra | 4b85d46 | 2018-12-16 13:10:58 +0530 | [diff] [blame] | 3 | #include <baseboard/variants.h> |
Furquan Shaikh | 7418464 | 2019-03-11 20:22:59 -0700 | [diff] [blame] | 4 | #include <ec/google/chromeec/ec.h> |
Philip Chen | 0d4200f | 2019-04-29 10:18:24 -0700 | [diff] [blame] | 5 | #include <gpio.h> |
Furquan Shaikh | 7418464 | 2019-03-11 20:22:59 -0700 | [diff] [blame] | 6 | #include <memory_info.h> |
Aamir Bohra | 4b85d46 | 2018-12-16 13:10:58 +0530 | [diff] [blame] | 7 | #include <soc/cnl_memcfg_init.h> |
Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 8 | #include <soc/romstage.h> |
Aamir Bohra | d3c5544 | 2019-06-16 19:38:45 +0530 | [diff] [blame] | 9 | #include <variant/gpio.h> |
Philip Chen | 0d4200f | 2019-04-29 10:18:24 -0700 | [diff] [blame] | 10 | |
| 11 | /* |
| 12 | * GPIO_MEM_CH_SEL is set to 1 for single channel skus |
| 13 | * and 0 for dual channel skus. |
| 14 | */ |
| 15 | #define GPIO_MEM_CH_SEL GPP_F2 |
| 16 | |
Furquan Shaikh | 463fca4 | 2019-07-11 22:38:42 -0700 | [diff] [blame] | 17 | int __weak variant_memory_sku(void) |
Philip Chen | 0d4200f | 2019-04-29 10:18:24 -0700 | [diff] [blame] | 18 | { |
| 19 | const gpio_t spd_gpios[] = { |
| 20 | GPIO_MEM_CONFIG_0, |
| 21 | GPIO_MEM_CONFIG_1, |
| 22 | GPIO_MEM_CONFIG_2, |
| 23 | GPIO_MEM_CONFIG_3, |
| 24 | }; |
| 25 | |
| 26 | return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); |
| 27 | } |
| 28 | |
Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 29 | void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 30 | { |
Shelley Chen | 2ee720c | 2019-02-11 13:06:10 -0800 | [diff] [blame] | 31 | struct cnl_mb_cfg memcfg; |
Philip Chen | 0d4200f | 2019-04-29 10:18:24 -0700 | [diff] [blame] | 32 | int mem_sku; |
| 33 | int is_single_ch_mem; |
Aamir Bohra | 4b85d46 | 2018-12-16 13:10:58 +0530 | [diff] [blame] | 34 | |
Shelley Chen | 2ee720c | 2019-02-11 13:06:10 -0800 | [diff] [blame] | 35 | variant_memory_params(&memcfg); |
Furquan Shaikh | 463fca4 | 2019-07-11 22:38:42 -0700 | [diff] [blame] | 36 | mem_sku = variant_memory_sku(); |
Philip Chen | 0d4200f | 2019-04-29 10:18:24 -0700 | [diff] [blame] | 37 | /* |
| 38 | * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single |
| 39 | * channel skus and 0 for dual channel skus. |
| 40 | */ |
| 41 | is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); |
| 42 | |
| 43 | /* |
| 44 | * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. |
| 45 | * Dual-DIMM memory is not used in hatch family, so we only |
| 46 | * fill in spd_info for CH0D0 and CH1D0 here. |
| 47 | */ |
| 48 | memcfg.spd[0].read_type = READ_SPD_CBFS; |
| 49 | memcfg.spd[0].spd_spec.spd_index = mem_sku; |
| 50 | if (!is_single_ch_mem) { |
| 51 | memcfg.spd[2].read_type = READ_SPD_CBFS; |
| 52 | memcfg.spd[2].spd_spec.spd_index = mem_sku; |
| 53 | } |
| 54 | |
| 55 | cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); |
Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 56 | } |