| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 1 | FLASH@0xfe000000 0x2000000 { |
| V Sowmya | 656015c | 2018-12-24 09:34:15 +0530 | [diff] [blame] | 2 | SI_ALL@0x0 0x400000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 3 | SI_DESC@0x0 0x1000 |
| V Sowmya | 656015c | 2018-12-24 09:34:15 +0530 | [diff] [blame] | 4 | SI_ME@0x1000 0x3ff000 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 5 | } |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 6 | SI_BIOS@0x400000 0x1c00000 { |
| 7 | # Place RW_LEGACY at the start of BIOS region such that the rest |
| 8 | # of BIOS regions start at 16MiB boundary. Since this is a 32MiB |
| 9 | # SPI flash only the top 16MiB actually gets memory mapped. |
| 10 | RW_LEGACY(CBFS)@0x0 0x1000000 |
| 11 | RW_SECTION_A@0x1000000 0x3e0000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 12 | VBLOCK_A@0x0 0x10000 |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 13 | FW_MAIN_A(CBFS)@0x10000 0x3cffc0 |
| 14 | RW_FWID_A@0x3dffc0 0x40 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 15 | } |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 16 | RW_SECTION_B@0x13e0000 0x3e0000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 17 | VBLOCK_B@0x0 0x10000 |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 18 | FW_MAIN_B(CBFS)@0x10000 0x3cffc0 |
| 19 | RW_FWID_B@0x3dffc0 0x40 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 20 | } |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 21 | RW_MISC@0x17c0000 0x40000 { |
| Shelley Chen | 62e79d2 | 2019-10-04 12:38:47 -0700 | [diff] [blame] | 22 | UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 23 | RECOVERY_MRC_CACHE@0x0 0x10000 |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 24 | RW_MRC_CACHE@0x10000 0x20000 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 25 | } |
| Hung-Te Lin | e586182 | 2019-03-04 16:48:05 +0800 | [diff] [blame] | 26 | RW_ELOG(PRESERVE)@0x30000 0x4000 |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 27 | RW_SHARED@0x34000 0x4000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 28 | SHARED_DATA@0x0 0x2000 |
| 29 | VBLOCK_DEV@0x2000 0x2000 |
| 30 | } |
| Hung-Te Lin | e586182 | 2019-03-04 16:48:05 +0800 | [diff] [blame] | 31 | RW_VPD(PRESERVE)@0x38000 0x2000 |
| 32 | RW_NVRAM(PRESERVE)@0x3a000 0x6000 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 33 | } |
| Subrata Banik | e2c653e | 2018-12-31 16:23:44 +0530 | [diff] [blame] | 34 | # Make WP_RO region align with SPI vendor |
| 35 | # memory protected range specification. |
| Furquan Shaikh | 32bc1dc | 2019-02-12 08:15:47 -0800 | [diff] [blame] | 36 | WP_RO@0x1800000 0x400000 { |
| Hung-Te Lin | e586182 | 2019-03-04 16:48:05 +0800 | [diff] [blame] | 37 | RO_VPD(PRESERVE)@0x0 0x4000 |
| Subrata Banik | e2c653e | 2018-12-31 16:23:44 +0530 | [diff] [blame] | 38 | RO_SECTION@0x4000 0x3fc000 { |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 39 | FMAP@0x0 0x800 |
| 40 | RO_FRID@0x800 0x40 |
| 41 | RO_FRID_PAD@0x840 0x7c0 |
| Hung-Te Lin | 064d6cb | 2019-10-17 12:42:28 +0800 | [diff] [blame] | 42 | GBB@0x1000 0x3000 |
| 43 | COREBOOT(CBFS)@0x4000 0x3f8000 |
| Shelley Chen | e3110b8 | 2018-12-10 12:59:01 -0800 | [diff] [blame] | 44 | } |
| 45 | } |
| 46 | } |
| 47 | } |