| Tracy Wu | cae27eb | 2022-02-09 10:34:12 +0800 | [diff] [blame] | 1 | FLASH 32M { |
| 2 | SI_ALL 5M { |
| 3 | SI_DESC 4K |
| 4 | SI_ME { |
| 5 | CSE_LAYOUT 8K |
| 6 | CSE_RO 1588K |
| 7 | CSE_DATA 512K |
| 8 | # 64-KiB aligned to optimize RW erases during CSE update. |
| 9 | CSE_RW 3008K |
| 10 | } |
| 11 | } |
| 12 | SI_BIOS 27M { |
| 13 | RW_SECTION_A 8M { |
| 14 | VBLOCK_A 64K |
| 15 | FW_MAIN_A(CBFS) |
| 16 | RW_FWID_A 64 |
| 17 | ME_RW_A(CBFS) 3008K |
| 18 | } |
| 19 | RW_LEGACY(CBFS) 2M |
| 20 | RW_MISC 1M { |
| 21 | UNIFIED_MRC_CACHE(PRESERVE) 128K { |
| 22 | RECOVERY_MRC_CACHE 64K |
| 23 | RW_MRC_CACHE 64K |
| 24 | } |
| 25 | RW_ELOG(PRESERVE) 16K |
| 26 | RW_SHARED 16K { |
| 27 | SHARED_DATA 8K |
| 28 | VBLOCK_DEV 8K |
| 29 | } |
| 30 | # The RW_SPD_CACHE region is only used for brya variants that use DDRx memory. |
| 31 | # It is placed in the common `chromeos.fmd` file because it is only 4K and there |
| 32 | # is free space in the RW_MISC region that cannot be easily reclaimed because |
| 33 | # the RW_SECTION_B must start on the 16M boundary. |
| 34 | RW_SPD_CACHE(PRESERVE) 4K |
| 35 | RW_VPD(PRESERVE) 8K |
| 36 | RW_NVRAM(PRESERVE) 24K |
| 37 | } |
| 38 | # This section starts at the 16M boundary in SPI flash. |
| 39 | # ADL does not support a region crossing this boundary, |
| 40 | # because the SPI flash is memory-mapped into two non- |
| 41 | # contiguous windows. |
| 42 | RW_SECTION_B 8M { |
| 43 | VBLOCK_B 64K |
| 44 | FW_MAIN_B(CBFS) |
| 45 | RW_FWID_B 64 |
| 46 | ME_RW_B(CBFS) 3008K |
| 47 | } |
| 48 | # Make WP_RO region align with SPI vendor |
| 49 | # memory protected range specification. |
| 50 | WP_RO 8M { |
| 51 | RO_VPD(PRESERVE) 16K |
| 52 | RO_SECTION { |
| 53 | FMAP 2K |
| 54 | RO_FRID 64 |
| 55 | GBB@4K 448K |
| 56 | COREBOOT(CBFS) |
| 57 | } |
| 58 | } |
| 59 | } |
| 60 | } |