Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007 AMD |
| 5 | ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 6 | ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> |
| 7 | ## (Thanks to LSRA University of Mannheim for their support) |
| 8 | ## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net> |
| 9 | ## |
| 10 | ## This program is free software; you can redistribute it and/or modify |
| 11 | ## it under the terms of the GNU General Public License as published by |
| 12 | ## the Free Software Foundation; either version 2 of the License, or |
| 13 | ## (at your option) any later version. |
| 14 | ## |
| 15 | ## This program is distributed in the hope that it will be useful, |
| 16 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | ## GNU General Public License for more details. |
| 19 | ## |
| 20 | ## You should have received a copy of the GNU General Public License |
| 21 | ## along with this program; if not, write to the Free Software |
| 22 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 23 | ## |
| 24 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 25 | ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| 26 | default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
Carl-Daniel Hailfinger | b5e10bc | 2009-04-21 00:16:06 +0000 | [diff] [blame] | 27 | include /config/failovercalculation.lb |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 28 | |
| 29 | arch i386 end |
| 30 | |
| 31 | ## |
| 32 | ## Build the objects we have code for in this directory. |
| 33 | ## |
| 34 | |
| 35 | driver mainboard.o |
| 36 | |
| 37 | #dir /drivers/ati/ragexl |
| 38 | |
| 39 | # Needed by irq_tables and mptable and acpi_tables. |
| 40 | object get_bus_conf.o |
| 41 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 42 | if CONFIG_GENERATE_MP_TABLE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 43 | object mptable.o |
| 44 | end |
| 45 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 46 | if CONFIG_GENERATE_PIRQ_TABLE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 47 | object irq_tables.o |
| 48 | end |
| 49 | |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 50 | if CONFIG_USE_INIT |
| 51 | makerule ./auto.o |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 52 | depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 53 | action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 54 | end |
| 55 | else |
| 56 | makerule ./auto.inc |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 57 | depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 58 | action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
Stefan Reinauer | 4ed326b | 2008-11-28 12:09:17 +0000 | [diff] [blame] | 59 | action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
| 60 | action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 61 | end |
| 62 | end |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 63 | |
| 64 | ## |
| 65 | ## Build our 16 bit and 32 bit coreboot entry code. |
| 66 | ## |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 67 | if CONFIG_HAVE_FAILOVER_BOOT |
| 68 | if CONFIG_USE_FAILOVER_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 69 | mainboardinit cpu/x86/16bit/entry16.inc |
| 70 | ldscript /cpu/x86/16bit/entry16.lds |
| 71 | end |
| 72 | else |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 73 | if CONFIG_USE_FALLBACK_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 74 | mainboardinit cpu/x86/16bit/entry16.inc |
| 75 | ldscript /cpu/x86/16bit/entry16.lds |
| 76 | end |
| 77 | end |
| 78 | |
| 79 | mainboardinit cpu/x86/32bit/entry32.inc |
| 80 | |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 81 | if CONFIG_USE_INIT |
| 82 | ldscript /cpu/x86/32bit/entry32.lds |
| 83 | ldscript /cpu/amd/car/cache_as_ram.lds |
| 84 | end |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 85 | |
| 86 | ## |
| 87 | ## Build our reset vector (this is where coreboot is entered). |
| 88 | ## |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 89 | if CONFIG_HAVE_FAILOVER_BOOT |
| 90 | if CONFIG_USE_FAILOVER_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 91 | mainboardinit cpu/x86/16bit/reset16.inc |
| 92 | ldscript /cpu/x86/16bit/reset16.lds |
| 93 | else |
| 94 | mainboardinit cpu/x86/32bit/reset32.inc |
| 95 | ldscript /cpu/x86/32bit/reset32.lds |
| 96 | end |
| 97 | else |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 98 | if CONFIG_USE_FALLBACK_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 99 | mainboardinit cpu/x86/16bit/reset16.inc |
| 100 | ldscript /cpu/x86/16bit/reset16.lds |
| 101 | else |
| 102 | mainboardinit cpu/x86/32bit/reset32.inc |
| 103 | ldscript /cpu/x86/32bit/reset32.lds |
| 104 | end |
| 105 | end |
| 106 | |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 107 | ## |
| 108 | ## Include an ID string (for safe flashing). |
| 109 | ## |
Patrick Georgi | 436f99b | 2009-11-27 16:55:13 +0000 | [diff] [blame^] | 110 | mainboardinit arch/i386/lib/id.inc |
| 111 | ldscript /arch/i386/lib/id.lds |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 112 | |
| 113 | ## |
| 114 | ## ROMSTRAP table for CK804 |
| 115 | ## |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 116 | if CONFIG_HAVE_FAILOVER_BOOT |
| 117 | if CONFIG_USE_FAILOVER_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 118 | mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| 119 | ldscript /southbridge/nvidia/ck804/romstrap.lds |
| 120 | end |
| 121 | else |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 122 | if CONFIG_USE_FALLBACK_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 123 | mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| 124 | ldscript /southbridge/nvidia/ck804/romstrap.lds |
| 125 | end |
| 126 | end |
| 127 | |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 128 | ## |
| 129 | ## Setup Cache-As-Ram |
| 130 | ## |
| 131 | mainboardinit cpu/amd/car/cache_as_ram.inc |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 132 | |
| 133 | ### |
| 134 | ### This is the early phase of coreboot startup. |
| 135 | ### Things are delicate and we test to see if we should |
| 136 | ### failover to another image. |
| 137 | ### |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 138 | if CONFIG_HAVE_FAILOVER_BOOT |
| 139 | if CONFIG_USE_FAILOVER_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 140 | ldscript /arch/i386/lib/failover_failover.lds |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 141 | end |
| 142 | else |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 143 | if CONFIG_USE_FALLBACK_IMAGE |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 144 | ldscript /arch/i386/lib/failover.lds |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 145 | end |
| 146 | end |
| 147 | |
| 148 | ### |
| 149 | ### O.k. We aren't just an intermediary anymore! |
| 150 | ### |
| 151 | |
| 152 | ## |
| 153 | ## Setup RAM |
| 154 | ## |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 155 | if CONFIG_USE_INIT |
| 156 | initobject auto.o |
| 157 | else |
| 158 | mainboardinit ./auto.inc |
| 159 | end |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 160 | |
| 161 | ## |
| 162 | ## Include the secondary configuration files |
| 163 | ## |
Stefan Reinauer | 3081bdf | 2009-04-01 13:43:21 +0000 | [diff] [blame] | 164 | config chip.h |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 165 | |
| 166 | chip northbridge/amd/amdk8/root_complex # Root complex |
| 167 | device apic_cluster 0 on # APIC cluster |
| 168 | chip cpu/amd/socket_754 # Socket 754 CPU |
| 169 | device apic 0 on end # APIC |
| 170 | end |
| 171 | end |
| 172 | |
| 173 | device pci_domain 0 on # PCI domain |
| 174 | chip northbridge/amd/amdk8 # mc0 |
| 175 | device pci 18.0 on # Northbridge |
| 176 | # Devices on link 0, link 0 == LDT 0 |
| 177 | chip southbridge/nvidia/ck804 # Southbridge |
| 178 | device pci 0.0 on end # HT |
| 179 | device pci 1.0 on # LPC |
| 180 | chip superio/winbond/w83627thf # Super I/O |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 181 | device pnp 4e.0 on # Floppy |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 182 | io 0x60 = 0x3f0 |
| 183 | irq 0x70 = 6 |
| 184 | drq 0x74 = 2 |
| 185 | end |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 186 | device pnp 4e.1 on # Parallel port |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 187 | io 0x60 = 0x378 |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 188 | irq 0x70 = 7 |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 189 | end |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 190 | device pnp 4e.2 on # Com1 |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 191 | io 0x60 = 0x3f8 |
| 192 | irq 0x70 = 4 |
| 193 | end |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 194 | device pnp 4e.3 on # Com2 |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 195 | io 0x60 = 0x2f8 |
| 196 | irq 0x70 = 3 |
| 197 | end |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 198 | device pnp 4e.5 on # PS/2 keyboard |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 199 | io 0x60 = 0x60 |
| 200 | io 0x62 = 0x64 |
| 201 | irq 0x70 = 1 |
| 202 | irq 0x72 = 12 |
| 203 | end |
Jonathan A. Kollasch | 4f91417 | 2008-05-06 13:26:32 +0000 | [diff] [blame] | 204 | device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 |
| 205 | device pnp 4e.8 off end # GPIO 2 |
| 206 | device pnp 4e.9 off end # GPIO 3, GPIO 4 |
| 207 | device pnp 4e.a off end # ACPI |
| 208 | device pnp 4e.b on # Hardware monitor |
Jonathan A. Kollasch | 8eff1e3 | 2008-02-20 15:59:30 +0000 | [diff] [blame] | 209 | io 0x60 = 0x290 |
| 210 | irq 0x70 = 0 |
| 211 | end |
| 212 | end |
| 213 | end |
| 214 | device pci 1.1 on end # SMbus |
| 215 | device pci 2.0 on end # USB 1.1 |
| 216 | device pci 2.1 on end # USB 2 |
| 217 | device pci 4.0 on end # Onboard audio (ACI) |
| 218 | device pci 4.1 off end # Onboard modem (MCI) -- not wired out |
| 219 | device pci 6.0 on end # IDE |
| 220 | device pci 7.0 on end # SATA 1 |
| 221 | device pci 8.0 on end # SATA 0 |
| 222 | device pci 9.0 on end # PCI |
| 223 | device pci a.0 on end # NIC |
| 224 | device pci b.0 off end # PCI E 3 -- not wired out |
| 225 | device pci c.0 off end # PCI E 2 -- not wired out |
| 226 | device pci d.0 on end # PCI E 1 |
| 227 | device pci e.0 on end # PCI E 0 |
| 228 | register "ide0_enable" = "1" |
| 229 | register "ide1_enable" = "1" |
| 230 | register "sata0_enable" = "1" |
| 231 | register "sata1_enable" = "1" |
| 232 | # register "mac_eeprom_smbus" = "3" |
| 233 | # register "mac_eeprom_addr" = "0x51" |
| 234 | end |
| 235 | end |
| 236 | device pci 18.1 on end |
| 237 | device pci 18.2 on end |
| 238 | device pci 18.3 on end |
| 239 | end |
| 240 | end |
| 241 | end |