Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci_ops.h> |
| 6 | #include <intelblocks/pmc.h> |
| 7 | #include <intelblocks/pmclib.h> |
| 8 | #include <intelblocks/rtc.h> |
| 9 | #include <reg_script.h> |
| 10 | #include <soc/pci_devs.h> |
| 11 | #include <soc/pm.h> |
| 12 | |
Angel Pons | 6a2ece7 | 2021-04-17 13:30:40 +0200 | [diff] [blame] | 13 | #include "chip.h" |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 14 | |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 15 | /* Fill up PMC resource structure */ |
| 16 | int pmc_soc_get_resources(struct pmc_resource_config *cfg) |
| 17 | { |
| 18 | cfg->pwrmbase_offset = PWRMBASE; |
| 19 | cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; |
| 20 | cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; |
| 21 | cfg->abase_offset = ABASE; |
| 22 | cfg->abase_addr = ACPI_BASE_ADDRESS; |
| 23 | cfg->abase_size = ACPI_BASE_SIZE; |
| 24 | |
| 25 | return 0; |
| 26 | } |
| 27 | |
| 28 | static const struct reg_script pch_pmc_misc_init_script[] = { |
| 29 | /* Enable SCI and clear SLP requests. */ |
| 30 | REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), |
Jonathan Zhang | 43277976 | 2023-01-23 10:55:09 -0800 | [diff] [blame^] | 31 | REG_SCRIPT_END}; |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 32 | |
| 33 | static const struct reg_script pmc_write1_to_clear_script[] = { |
| 34 | REG_PCI_OR32(GEN_PMCON_A, 0), |
| 35 | REG_PCI_OR32(GEN_PMCON_B, 0), |
| 36 | REG_PCI_OR32(GEN_PMCON_B, 0), |
| 37 | REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), |
| 38 | REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), |
Jonathan Zhang | 43277976 | 2023-01-23 10:55:09 -0800 | [diff] [blame^] | 39 | REG_SCRIPT_END}; |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 40 | |
| 41 | void pmc_soc_init(struct device *dev) |
| 42 | { |
| 43 | pmc_set_power_failure_state(true); |
| 44 | pmc_gpe_init(); |
| 45 | |
| 46 | /* Note that certain bits may be cleared from running script as |
| 47 | * certain bit fields are write 1 to clear. */ |
| 48 | reg_script_run_on_dev(dev, pch_pmc_misc_init_script); |
| 49 | pmc_set_acpi_mode(); |
| 50 | |
| 51 | /* Clear registers that contain write-1-to-clear bits. */ |
| 52 | reg_script_run_on_dev(dev, pmc_write1_to_clear_script); |
| 53 | } |