Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| 3 | |
| 4 | #ifndef __AMD_PSP_DEF_H__ |
| 5 | #define __AMD_PSP_DEF_H__ |
| 6 | |
| 7 | #include <types.h> |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 8 | #include <commonlib/helpers.h> |
Marshall Dawson | e8ffa9f | 2020-03-16 19:20:20 -0600 | [diff] [blame] | 9 | #include <amdblocks/psp.h> |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 10 | |
| 11 | /* x86 to PSP commands */ |
Felix Held | 43126ed | 2020-04-01 22:06:39 +0200 | [diff] [blame^] | 12 | #define MBOX_BIOS_CMD_DRAM_INFO 0x01 |
| 13 | #define MBOX_BIOS_CMD_SMM_INFO 0x02 |
| 14 | #define MBOX_BIOS_CMD_SX_INFO 0x03 |
| 15 | #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 |
| 16 | #define MBOX_BIOS_CMD_RSM_INFO 0x04 |
| 17 | #define MBOX_BIOS_CMD_PSP_QUERY 0x05 |
| 18 | #define MBOX_BIOS_CMD_BOOT_DONE 0x06 |
| 19 | #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 |
| 20 | #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 |
| 21 | #define MBOX_BIOS_CMD_NOP 0x09 |
| 22 | #define MBOX_BIOS_CMD_SMU_FW 0x19 |
| 23 | #define MBOX_BIOS_CMD_SMU_FW2 0x1a |
| 24 | #define MBOX_BIOS_CMD_ABORT 0xfe |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 25 | |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 26 | /* generic PSP interface status, v1 */ |
| 27 | #define PSPV1_STATUS_INITIALIZED BIT(0) |
| 28 | #define PSPV1_STATUS_ERROR BIT(1) |
| 29 | #define PSPV1_STATUS_TERMINATED BIT(2) |
| 30 | #define PSPV1_STATUS_HALT BIT(3) |
| 31 | #define PSPV1_STATUS_RECOVERY BIT(4) |
| 32 | |
| 33 | /* generic PSP interface status, v2 */ |
| 34 | #define PSPV2_STATUS_ERROR BIT(30) |
| 35 | #define PSPV2_STATUS_RECOVERY BIT(31) |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 36 | |
| 37 | /* psp_mbox consists of hardware registers beginning at PSPx000070 |
| 38 | * mbox_command: BIOS->PSP command, cleared by PSP when complete |
| 39 | * mbox_status: BIOS->PSP interface status |
| 40 | * cmd_response: pointer to command/response buffer |
| 41 | */ |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 42 | struct pspv1_mbox { |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 43 | u32 mbox_command; |
| 44 | u32 mbox_status; |
| 45 | u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ |
| 46 | } __packed; |
| 47 | |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 48 | struct pspv2_mbox { |
| 49 | union { |
| 50 | u32 val; |
| 51 | struct pspv2_mbox_cmd_fields { |
| 52 | u16 mbox_status; |
| 53 | u8 mbox_command; |
| 54 | u32 reserved:6; |
| 55 | u32 recovery:1; |
| 56 | u32 ready:1; |
| 57 | } __packed fields; |
| 58 | }; |
| 59 | u64 cmd_response; |
| 60 | } __packed; |
| 61 | |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 62 | /* command/response format, BIOS builds this in memory |
| 63 | * mbox_buffer_header: generic header |
| 64 | * mbox_buffer: command-specific buffer format |
| 65 | * |
| 66 | * AMD reference code aligns and pads all buffers to 32 bytes. |
| 67 | */ |
| 68 | struct mbox_buffer_header { |
| 69 | u32 size; /* total size of buffer */ |
| 70 | u32 status; /* command status, filled by PSP if applicable */ |
| 71 | } __packed; |
| 72 | |
| 73 | /* |
| 74 | * command-specific buffer definitions: see NDA document #54267 |
| 75 | * The following commands need a buffer definition if they are to be used. |
| 76 | * All other commands will work with the default buffer. |
| 77 | * MBOX_BIOS_CMD_SMM_INFO MBOX_BIOS_CMD_PSP_QUERY |
| 78 | * MBOX_BIOS_CMD_SX_INFO MBOX_BIOS_CMD_S3_DATA_INFO |
| 79 | * MBOX_BIOS_CMD_RSM_INFO |
| 80 | */ |
| 81 | |
| 82 | struct mbox_default_buffer { /* command-response buffer unused by command */ |
| 83 | struct mbox_buffer_header header; |
| 84 | } __attribute__((packed, aligned(32))); |
| 85 | |
Marshall Dawson | e8ffa9f | 2020-03-16 19:20:20 -0600 | [diff] [blame] | 86 | struct smm_req_buffer { |
| 87 | uint64_t smm_base; /* TSEG base */ |
| 88 | uint64_t smm_mask; /* TSEG mask */ |
| 89 | uint64_t psp_smm_data_region; /* PSP region in SMM space */ |
| 90 | uint64_t psp_smm_data_length; /* PSP region length in SMM space */ |
| 91 | struct smm_trigger_info smm_trig_info; |
| 92 | #if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) |
| 93 | struct smm_register_info smm_reg_info; |
| 94 | #endif |
| 95 | uint64_t psp_mbox_smm_buffer_address; |
| 96 | uint64_t psp_mbox_smm_flag_address; |
| 97 | } __packed; |
| 98 | |
| 99 | struct mbox_cmd_smm_info_buffer { |
| 100 | struct mbox_buffer_header header; |
| 101 | struct smm_req_buffer req; |
| 102 | } __attribute__((packed, aligned(32))); |
| 103 | |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 104 | struct mbox_cmd_sx_info_buffer { |
| 105 | struct mbox_buffer_header header; |
| 106 | u8 sleep_type; |
| 107 | } __attribute__((packed, aligned(32))); |
| 108 | |
| 109 | #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ |
| 110 | #define PSP_CMD_TIMEOUT 1000 /* 1 second */ |
| 111 | |
Felix Held | 1ad7392 | 2020-04-14 02:07:19 +0200 | [diff] [blame] | 112 | void psp_print_cmd_status(int cmd_status, struct mbox_default_buffer *buffer); |
| 113 | |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 114 | /* This command needs to be implemented by the generation specific code. */ |
| 115 | int send_psp_command(u32 command, void *buffer); |
| 116 | |
Marshall Dawson | 3c57819 | 2020-01-19 17:16:01 -0700 | [diff] [blame] | 117 | #endif /* __AMD_PSP_DEF_H__ */ |