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review.coreboot.org / coreboot / 43105d6a5a4898386e35c4fdccdf643b95faef98 / . / src / cpu / Kconfig
blob: acb9bb5d0aef8ed13c5a7b871e6bc271ff058830 [file] [log] [blame]
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000[diff] [blame]1if ARCH_X86
2
Ronald G. Minnich5f6572e2009-08-12 15:39:38 +0000[diff] [blame]3source src/cpu/amd/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]4source src/cpu/intel/Kconfig
5source src/cpu/via/Kconfig
6source src/cpu/x86/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]7
Stefan Reinauer704b5962010-08-30 17:53:13 +0000[diff] [blame]8config CACHE_AS_RAM
Patrick Georgi39ec29c2009-08-27 12:10:50 +0000[diff] [blame]9 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +0000[diff] [blame]10 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +0000[diff] [blame]11
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]12config DCACHE_RAM_BASE
13 hex
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]14
15config DCACHE_RAM_SIZE
16 hex
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]17
Patrick Georgi88f55b22009-09-25 18:43:02 +0000[diff] [blame]18config DCACHE_RAM_GLOBAL_VAR_SIZE
19 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000[diff] [blame]20 default 0x0
Patrick Georgi88f55b22009-09-25 18:43:02 +0000[diff] [blame]21
Stefan Reinauer2c41c402012-05-01 11:13:52 -0700[diff] [blame]22# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
23# yet be dropped completely.
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]24config MAX_PHYSICAL_CPUS
25 int
26 default 1
27
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]28config SMP
29 bool
Myles Watson45bb25f2009-09-22 18:49:08 +0000[diff] [blame]30 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +0000[diff] [blame]31 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +0000[diff] [blame]32 help
33 This option is used to enable certain functions to make coreboot
34 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +0000[diff] [blame]35
Kyösti Mälkki7dfe32c2012-02-14 10:39:17 +0200[diff] [blame]36config AP_SIPI_VECTOR
37 hex
38 default 0xfffff000
39 help
40 This must equal address of ap_sipi_vector from bootblock build.
Patrick Georgi819c7d42012-03-31 13:08:12 +0200[diff] [blame]41
Ronald G. Minnich149d6752009-10-01 23:22:50 +0000[diff] [blame]42config MMX
43 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]44 help
45 Select MMX in your socket or model Kconfig if your CPU has MMX
46 streaming SIMD instructions. ROMCC can build more efficient
47 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +0000[diff] [blame]48
49config SSE
50 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]51 help
52 Select SSE in your socket or model Kconfig if your CPU has SSE
53 streaming SIMD instructions. ROMCC can build more efficient
54 code if it can spill to SSE (aka XMM) registers.
55
56config SSE2
57 bool
Myles Watson34261952010-03-19 02:33:40 +0000[diff] [blame]58 default n
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]59 help
60 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
61 streaming SIMD instructions. Some parts of coreboot can be built
62 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]63
64config VAR_MTRR_HOLE
65 bool
66 default y
67 help
68 Unset this if you don't want the MTRR code to use
69 subtractive MTRRs
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000[diff] [blame]70
71endif # ARCH_X86