| Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, |
| 9 | * so the bootblock loading address must be placed after that. After the |
| 10 | * handoff that area may be reclaimed for other uses, e.g. CBFS cache. |
| 11 | * TODO: Did this change on Tegra210? What's the new valid range? |
| 12 | */ |
| 13 | |
| 14 | SECTIONS |
| 15 | { |
| 16 | SRAM_START(0x40000000) |
| Philipp Deppenwiese | c9b7d1f | 2018-11-10 00:35:02 +0100 | [diff] [blame] | 17 | PRERAM_CBMEM_CONSOLE(0x40000000, 2K) |
| Julius Werner | cefe89e | 2019-11-06 19:29:44 -0800 | [diff] [blame] | 18 | FMAP_CACHE(0x40000800, 2K) |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 19 | PRERAM_CBFS_CACHE(0x40001000, 20K) |
| 20 | CBFS_MCACHE(0x40006000, 8K) |
| Christian Walter | 6d2dbe1 | 2019-07-31 16:23:53 +0200 | [diff] [blame] | 21 | VBOOT2_WORK(0x40008000, 12K) |
| Sergii Dmytruk | 2710df7 | 2022-11-10 00:40:51 +0200 | [diff] [blame] | 22 | TPM_LOG(0x4000B000, 2K) |
| Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 23 | #if ENV_ARM64 |
| Christian Walter | 6d2dbe1 | 2019-07-31 16:23:53 +0200 | [diff] [blame] | 24 | STACK(0x4000B800, 3K) |
| Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 25 | #else /* AVP gets a separate stack to avoid any chance of handoff races. */ |
| Christian Walter | 6d2dbe1 | 2019-07-31 16:23:53 +0200 | [diff] [blame] | 26 | STACK(0x4000C400, 3K) |
| Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 27 | #endif |
| Christian Walter | 6d2dbe1 | 2019-07-31 16:23:53 +0200 | [diff] [blame] | 28 | TIMESTAMP(0x4000D000, 2K) |
| Julius Werner | a2d123e | 2019-11-12 15:43:12 -0800 | [diff] [blame] | 29 | BOOTBLOCK(0x4000D800, 42K) |
| 30 | OVERLAP_VERSTAGE_ROMSTAGE(0x40018000, 160K) |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 31 | SRAM_END(0x40040000) |
| 32 | |
| 33 | DRAM_START(0x80000000) |
| 34 | POSTRAM_CBFS_CACHE(0x80100000, 1M) |
| Patrick Georgi | 42f1505 | 2023-10-07 11:16:43 +0200 | [diff] [blame^] | 35 | RAMSTAGE(0x80200000, 2M) |
| Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 36 | TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 37 | } |