| Angel Pons | 42d3005 | 2020-01-02 00:57:52 +0100 | [diff] [blame^] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2017 Bill Xie <persmule@gmail.com> |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; either version 2 of the License, or |
| 9 | # (at your option) any later version. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
| 16 | |
| 17 | chip northbridge/intel/sandybridge |
| 18 | register "gpu_cpu_backlight" = "0x00000263" |
| 19 | register "gpu_panel_power_backlight_off_delay" = "2000" |
| 20 | register "gpu_pch_backlight" = "0x02880288" |
| 21 | device domain 0x0 on |
| 22 | subsystemid 0x103c 0x18f8 inherit |
| 23 | |
| 24 | device pci 01.0 off end # PCIe Bridge for discrete graphics |
| 25 | device pci 02.0 on end # Internal graphics |
| 26 | |
| 27 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
| 28 | # mailbox at 0x200/0x201 and PM1 at 0x220 |
| 29 | register "gen1_dec" = "0x007c0201" |
| 30 | register "gen2_dec" = "0x000c0101" |
| 31 | register "gen3_dec" = "0x00fcfe01" |
| 32 | register "gen4_dec" = "0x000402e9" |
| 33 | register "gpi6_routing" = "2" |
| 34 | register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" |
| 35 | register "sata_port_map" = "0x1" |
| 36 | register "superspeed_capable_ports" = "0x0000000f" |
| 37 | register "xhci_overcurrent_mapping" = "0x00000c03" |
| 38 | register "xhci_switchable_ports" = "0x0000000f" |
| 39 | |
| 40 | device pci 14.0 on end # USB 3.0 Controller |
| 41 | device pci 1c.0 on end # PCIe Port #1 |
| 42 | device pci 1c.1 off end # PCIe Port #2 |
| 43 | device pci 1c.2 on end # PCIe Port #3 |
| 44 | device pci 1c.3 on end # PCIe Port #4 |
| 45 | device pci 1c.4 off end # PCIe Port #5 |
| 46 | device pci 1c.5 off end # PCIe Port #6 |
| 47 | device pci 1c.6 off end # PCIe Port #7 |
| 48 | device pci 1c.7 off end # PCIe Port #8 |
| 49 | device pci 1f.0 on # LPC bridge |
| 50 | chip ec/hp/kbc1126 |
| 51 | register "ec_data_port" = "0x62" |
| 52 | register "ec_cmd_port" = "0x66" |
| 53 | register "ec_ctrl_reg" = "0x81" |
| 54 | register "ec_fan_ctrl_value" = "0x70" |
| 55 | device pnp ff.1 off end |
| 56 | end |
| 57 | chip drivers/pc80/tpm |
| 58 | device pnp 0c31.0 on end |
| 59 | end |
| 60 | end |
| 61 | end |
| 62 | end |
| 63 | end |