src/mainboard/asus/p5gc-mx/devicetree.cb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/i945

	device cpu_cluster 0 on
		chip cpu/intel/socket_LGA775
			device lapic 0 on end
		end
		chip cpu/intel/model_1067x
			device lapic 0xACAC off end
		end
	end

	device domain 0 on
		device pci 00.0 on # host bridge
			subsystemid 0x1458 0x5000
		end
		device pci 01.0 on # i945 PCIe root port
			subsystemid 0x1458 0x5000
			ioapic_irq 2 INTA 0x10
		end
		device pci 02.0 on  # vga controller
			subsystemid 0x1458 0xd000
			ioapic_irq 2 INTA 0x10
		end

		chip southbridge/intel/i82801gx
			register "pirqa_routing" = "0x8b"
			register "pirqb_routing" = "0x8a"
			register "pirqc_routing" = "0x86"
			register "pirqd_routing" = "0x85"
			register "pirqe_routing" = "0x83"
			register "pirqf_routing" = "0x80"
			register "pirqg_routing" = "0x80"
			register "pirqh_routing" = "0x85"

			register "gpe0_en" = "0"

			register "ide_legacy_combined" = "0x0"
			register "ide_enable_primary" = "0x1"
			register "ide_enable_secondary" = "0x0"
			register "sata_ahci" = "0x0"

			register "p_cnt_throttling_supported" = "0"

			device pci 1b.0 on # High Definition Audio
				ioapic_irq 2 INTA 0x10
			end
			device pci 1c.0 on end # PCIe
			device pci 1c.1 on end # PCIe
			#device pci 1c.2 off end # PCIe port 3
			#device pci 1c.3 off end # PCIe port 4
			#device pci 1c.4 off end # PCIe port 5
			#device pci 1c.5 off end # PCIe port 6
			device pci 1d.0 on # USB UHCI
				ioapic_irq 2 INTA 0x10
			end
			device pci 1d.1 on # USB UHCI
				ioapic_irq 2 INTB 0x11
			end
			device pci 1d.2 on # USB UHCI
				ioapic_irq 2 INTC 0x12
			end
			device pci 1d.3 on # USB UHCI
				ioapic_irq 2 INTD 0x13
			end
			device pci 1d.7 on # USB2 EHCI
				ioapic_irq 2 INTA 0x10
			end
			device pci 1e.0 on end # PCI bridge

			device pci 1f.0 on # LPC bridge
				ioapic_irq 2 INTA 0x10
				chip superio/winbond/w83627dhg
					device pnp 2e.0 on # Floppy
						io 0x60 = 0x3f0
						irq 0x70 = 6
						drq 0x74 = 2
					end
					device pnp 2e.1 on # Parallel port
						io 0x60 = 0x378
						irq 0x70 = 7
						drq 0x74 = 3
					end
					device pnp 2e.2 on # COM1
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end
					device pnp 2e.3 on # COM2
						io 0x60 = 0x2f8
						irq 0x70 = 3
					end
					device pnp 2e.5 on # Keyboard
						io 0x60 = 0x60
						io 0x62 = 0x64
						irq 0x70 = 1 # Keyboard
						irq 0x72 = 12 # Mouse
					end
					device pnp 2e.6 off end # SPI
					device pnp 2e.7 on end # GPIO6
					device pnp 2e.8 off end # WDTO# & PLED
					device pnp 2e.9 off end # GPIO2
					device pnp 2e.109 on # GPIO3
						irq 0xf0 = 0xf3 # BSEL straps to output
						irq 0xf2 = 0x08 # INVERT GPIO33
					end
					device pnp 2e.209 on # GPIO4
						irq 0xf5 = 0xf8
					end
					device pnp 2e.309 on  # GPIO5
						irq 0xe0 = 0xde
					end
					device pnp 2e.a on # ACPI
						irq 0x70 = 0
						irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
					end
					device pnp 2e.b on # HWM
						io 0x60 = 0x290
						irq 0x70 = 0
					end
					device pnp 2e.c on end # PECI, SST
				end
			end
			device pci 1f.1 on # IDE
				ioapic_irq 2 INTB 0x11
			end
			device pci 1f.2 on # SATA
				ioapic_irq 2 INTC 0x12
			end
			device pci 1f.3 on # SMBus
				ioapic_irq 2 INTD 0x13
			end
		end
	end
end