Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/acpimmio.h> |
| 4 | #include <amdblocks/i2c.h> |
Kangheui Won | 62047e5 | 2021-04-15 17:34:09 +1000 | [diff] [blame] | 5 | #include <console/console.h> |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 6 | #include <soc/i2c.h> |
| 7 | #include <soc/southbridge.h> |
| 8 | #include "chip.h" |
| 9 | |
| 10 | #if ENV_X86 |
| 11 | static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { |
| 12 | { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, |
| 13 | { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, |
| 14 | { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, |
| 15 | { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" } |
| 16 | }; |
| 17 | #else |
Kangheui Won | 62047e5 | 2021-04-15 17:34:09 +1000 | [diff] [blame] | 18 | static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 19 | { I2C_MASTER_MODE, 0, "" }, |
| 20 | { I2C_MASTER_MODE, 0, "" }, |
| 21 | { I2C_MASTER_MODE, 0, "" }, |
| 22 | { I2C_MASTER_MODE, 0, "" } |
| 23 | }; |
| 24 | |
| 25 | void i2c_set_bar(unsigned int bus, uintptr_t bar) |
| 26 | { |
| 27 | if (bus >= ARRAY_SIZE(i2c_ctrlr)) { |
| 28 | printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); |
| 29 | return; |
| 30 | } |
| 31 | |
| 32 | i2c_ctrlr[bus].bar = bar; |
| 33 | } |
| 34 | #endif |
| 35 | |
| 36 | __weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } |
| 37 | |
| 38 | void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) |
| 39 | { |
Karthikeyan Ramasubramanian | fec4db9 | 2021-06-02 16:14:39 -0600 | [diff] [blame] | 40 | const struct soc_amd_cezanne_config *config = config_of_soc(); |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 41 | uint32_t pad_ctrl; |
| 42 | int misc_reg; |
| 43 | |
Karthikeyan Ramasubramanian | fec4db9 | 2021-06-02 16:14:39 -0600 | [diff] [blame] | 44 | if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) |
| 45 | return; |
| 46 | |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 47 | misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; |
| 48 | pad_ctrl = misc_read32(misc_reg); |
| 49 | |
| 50 | pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; |
| 51 | pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; |
| 52 | |
| 53 | pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; |
Karthikeyan Ramasubramanian | fec4db9 | 2021-06-02 16:14:39 -0600 | [diff] [blame] | 54 | pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus]; |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 55 | |
| 56 | pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; |
| 57 | pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? |
| 58 | I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; |
| 59 | pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; |
| 60 | |
| 61 | mainboard_i2c_override(bus, &pad_ctrl); |
| 62 | misc_write32(misc_reg, pad_ctrl); |
| 63 | } |
| 64 | |
| 65 | const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) |
| 66 | { |
| 67 | *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); |
| 68 | return i2c_ctrlr; |
| 69 | } |
| 70 | |
| 71 | const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) |
| 72 | { |
| 73 | const struct soc_amd_cezanne_config *config = config_of_soc(); |
| 74 | |
| 75 | *num_buses = ARRAY_SIZE(config->i2c); |
| 76 | return config->i2c; |
| 77 | } |