Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 41a2c73b064b6ab68e63dd8ce75ef07561d2857d / . / src / soc / amd / cezanne / chip.h
blob: 319ce4108e64703c6b9e4558f3ff0fe7caf5e85b [file] [log] [blame]
Felix Heldc8272782020-12-05 01:39:28 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef CEZANNE_CHIP_H
4#define CEZANNE_CHIP_H
5
6#include <amdblocks/chip.h>
Zheng Baob0f00ed2021-03-16 15:28:49 +0800[diff] [blame]7#include <soc/i2c.h>
Felix Held224b5782021-05-18 01:25:51 +0200[diff] [blame]8#include <soc/southbridge.h>
Zheng Baob0f00ed2021-03-16 15:28:49 +0800[diff] [blame]9#include <drivers/i2c/designware/dw_i2c.h>
Felix Held02bfbf42021-04-20 22:22:48 +0200[diff] [blame]10#include <types.h>
Julian Schroederd2f33082021-05-11 10:44:13 -0500[diff] [blame]11#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
Felix Heldc8272782020-12-05 01:39:28 +0100[diff] [blame]12
13struct soc_amd_cezanne_config {
14 struct soc_amd_common_config common_config;
Zheng Baob0f00ed2021-03-16 15:28:49 +0800[diff] [blame]15 u8 i2c_scl_reset;
16 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
Karthikeyan Ramasubramanianfec4db92021-06-02 16:14:39 -0600[diff] [blame]17 u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT];
Mathew King23cc1652021-04-14 15:29:44 -0600[diff] [blame]18
19 /* Enable S0iX support */
20 bool s0ix_enable;
Felix Heldd0b51642021-04-08 22:25:19 +0200[diff] [blame]21
22 enum {
23 DOWNCORE_AUTO = 0,
24 DOWNCORE_1 = 1, /* Run with 1 physical core */
25 DOWNCORE_2 = 3, /* Run with 2 physical cores */
26 DOWNCORE_3 = 4, /* Run with 3 physical cores */
27 DOWNCORE_4 = 6, /* Run with 4 physical cores */
28 DOWNCORE_5 = 8, /* Run with 5 physical cores */
29 DOWNCORE_6 = 9, /* Run with 6 physical cores */
30 DOWNCORE_7 = 10, /* Run with 7 physical cores */
31 } downcore_mode;
32 bool disable_smt; /* disable second thread on all physical cores */
Felix Heldd3be9ba2021-04-19 21:40:35 +0200[diff] [blame]33
34 uint8_t stt_control;
35 uint8_t stt_pcb_sensor_count;
36 uint16_t stt_min_limit;
37 uint16_t stt_m1;
38 uint16_t stt_m2;
39 uint16_t stt_m3;
40 uint16_t stt_m4;
41 uint16_t stt_m5;
42 uint16_t stt_m6;
43 uint16_t stt_c_apu;
44 uint16_t stt_c_gpu;
45 uint16_t stt_c_hs2;
46 uint16_t stt_alpha_apu;
47 uint16_t stt_alpha_gpu;
48 uint16_t stt_alpha_hs2;
49 uint16_t stt_skin_temp_apu;
50 uint16_t stt_skin_temp_gpu;
51 uint16_t stt_skin_temp_hs2;
52 uint16_t stt_error_coeff;
53 uint16_t stt_error_rate_coefficient;
54
55 uint8_t stapm_boost;
Martin Roth9c176652021-04-23 12:24:35 -0600[diff] [blame]56 uint32_t stapm_time_constant_s;
Felix Heldd3be9ba2021-04-19 21:40:35 +0200[diff] [blame]57 uint32_t apu_only_sppt_limit;
Martin Roth9c176652021-04-23 12:24:35 -0600[diff] [blame]58 uint32_t sustained_power_limit_mW;
59 uint32_t fast_ppt_limit_mW;
60 uint32_t slow_ppt_limit_mW;
Martin Roth029d9972021-04-23 12:22:59 -0600[diff] [blame]61 uint32_t slow_ppt_time_constant_s;
62 uint32_t thermctl_limit_degreeC;
Felix Heldd3be9ba2021-04-19 21:40:35 +0200[diff] [blame]63
64 uint8_t smartshift_enable;
65
66 uint8_t system_configuration;
67
68 uint8_t cppc_ctrl;
69 uint8_t cppc_perf_limit_max_range;
70 uint8_t cppc_perf_limit_min_range;
71 uint8_t cppc_epp_max_range;
72 uint8_t cppc_epp_min_range;
73 uint8_t cppc_preferred_cores;
Chris Wang06793922021-04-29 00:11:01 +0800[diff] [blame]74
75 /* telemetry settings */
76 uint32_t telemetry_vddcrvddfull_scale_current_mA;
77 uint32_t telemetry_vddcrvddoffset;
78 uint32_t telemetry_vddcrsocfull_scale_current_mA;
79 uint32_t telemetry_vddcrsocoffset;
80
Felix Held62682e72021-05-12 01:17:35 +0200[diff] [blame]81 /* Enable dptc for tablet mode (0 = disable, 1 = enable) */
82 uint8_t dptc_enable;
83
84 /* STAPM Configuration for tablet mode (need enable dptc_enable first) */
85 uint32_t fast_ppt_limit_tablet_mode_mW;
86 uint32_t slow_ppt_limit_tablet_mode_mW;
87 uint32_t sustained_power_limit_tablet_mode_mW;
88 uint32_t thermctl_limit_tablet_mode_degreeC;
Felix Held224b5782021-05-18 01:25:51 +0200[diff] [blame]89
90 /* The array index is the general purpose PCIe clock output number. Values in here
91 aren't the values written to the register to have the default to be always on. */
92 enum {
93 GPP_CLK_ON, /* GPP clock always on; default */
94 GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
95 GPP_CLK_OFF, /* GPP clk off */
96 } gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
Julian Schroederd2f33082021-05-11 10:44:13 -0500[diff] [blame]97
Felix Held9a24c3f2021-05-25 20:45:08 +0200[diff] [blame]98 /* performance policy for the PCIe links: power consumption vs. link speed */
99 enum {
100 DXIO_PSPP_PERFORMANCE = 0,
101 DXIO_PSPP_BALANCED,
102 DXIO_PSPP_POWERSAVE,
103 } pspp_policy;
104
Julian Schroederd2f33082021-05-11 10:44:13 -0500[diff] [blame]105 uint8_t usb_phy_custom;
106 struct usb_phy_config usb_phy;
Felix Heldc8272782020-12-05 01:39:28 +0100[diff] [blame]107};
108
109#endif /* CEZANNE_CHIP_H */