Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/amd_pci_mmconf.h> |
Felix Held | 2e1384a | 2021-02-12 15:49:06 +0100 | [diff] [blame] | 4 | #include <amdblocks/cpu.h> |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 5 | #include <bootblock_common.h> |
Felix Held | 1025203 | 2020-12-08 17:34:59 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
Felix Held | dffdea8 | 2020-12-09 23:04:29 +0100 | [diff] [blame] | 7 | #include <cpu/amd/mtrr.h> |
| 8 | #include <cpu/x86/cache.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/x86/mtrr.h> |
Felix Held | 4911c3e | 2020-12-08 17:39:26 +0100 | [diff] [blame] | 11 | #include <cpu/x86/tsc.h> |
Felix Held | dffdea8 | 2020-12-09 23:04:29 +0100 | [diff] [blame] | 12 | #include <soc/iomap.h> |
Felix Held | 153f92a | 2020-12-08 17:27:30 +0100 | [diff] [blame] | 13 | #include <soc/southbridge.h> |
Kangheui Won | dad067f | 2021-05-06 15:53:37 +1000 | [diff] [blame] | 14 | #include <soc/psp_transfer.h> |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 15 | #include <stdint.h> |
| 16 | |
Felix Held | dffdea8 | 2020-12-09 23:04:29 +0100 | [diff] [blame] | 17 | /* |
| 18 | * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. |
| 19 | * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses |
| 20 | * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. |
| 21 | */ |
| 22 | static void set_caching(void) |
| 23 | { |
| 24 | msr_t top_mem; |
| 25 | msr_t sys_cfg; |
| 26 | msr_t mtrr_def_type; |
| 27 | msr_t fixed_mtrr_ram; |
| 28 | msr_t fixed_mtrr_mmio; |
| 29 | struct var_mtrr_context mtrr_ctx; |
| 30 | |
| 31 | var_mtrr_context_init(&mtrr_ctx, NULL); |
| 32 | top_mem = rdmsr(TOP_MEM); |
| 33 | /* Enable RdDram and WrDram attributes in fixed MTRRs. */ |
| 34 | sys_cfg = rdmsr(SYSCFG_MSR); |
| 35 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 36 | |
| 37 | /* Fixed MTRR constants. */ |
| 38 | fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = |
| 39 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | |
| 40 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | |
| 41 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | |
| 42 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); |
| 43 | fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = |
| 44 | ((MTRR_TYPE_UNCACHEABLE) << 0) | |
| 45 | ((MTRR_TYPE_UNCACHEABLE) << 8) | |
| 46 | ((MTRR_TYPE_UNCACHEABLE) << 16) | |
| 47 | ((MTRR_TYPE_UNCACHEABLE) << 24); |
| 48 | |
| 49 | /* Prep default MTRR type. */ |
| 50 | mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); |
| 51 | mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; |
| 52 | mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; |
| 53 | mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; |
| 54 | |
| 55 | disable_cache(); |
| 56 | |
| 57 | wrmsr(SYSCFG_MSR, sys_cfg); |
| 58 | |
| 59 | clear_all_var_mtrr(); |
| 60 | |
| 61 | var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); |
| 62 | /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ |
| 63 | var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 64 | |
| 65 | /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ |
| 66 | wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); |
| 67 | wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); |
| 68 | wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); |
| 69 | wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); |
| 70 | wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); |
| 71 | wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); |
| 72 | wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); |
| 73 | wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); |
| 74 | wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); |
| 75 | wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); |
| 76 | wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); |
| 77 | |
| 78 | wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); |
| 79 | |
| 80 | /* Enable Fixed and Variable MTRRs. */ |
| 81 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; |
| 82 | sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; |
| 83 | /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once |
| 84 | MP init happens in coreboot proper it can be knocked down. */ |
| 85 | wrmsr(SYSCFG_MSR, sys_cfg); |
| 86 | |
| 87 | enable_cache(); |
| 88 | } |
| 89 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 90 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 91 | { |
Felix Held | dffdea8 | 2020-12-09 23:04:29 +0100 | [diff] [blame] | 92 | set_caching(); |
Felix Held | 2e1384a | 2021-02-12 15:49:06 +0100 | [diff] [blame] | 93 | write_resume_eip(); |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 94 | enable_pci_mmconf(); |
Felix Held | 4911c3e | 2020-12-08 17:39:26 +0100 | [diff] [blame] | 95 | |
| 96 | /* |
| 97 | * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz |
| 98 | * to get micro-seconds granularity. |
| 99 | */ |
| 100 | base_timestamp /= tsc_freq_mhz(); |
| 101 | |
| 102 | bootblock_main_with_basetime(base_timestamp); |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | void bootblock_soc_early_init(void) |
| 106 | { |
Felix Held | 153f92a | 2020-12-08 17:27:30 +0100 | [diff] [blame] | 107 | fch_pre_init(); |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | void bootblock_soc_init(void) |
| 111 | { |
Felix Held | 1025203 | 2020-12-08 17:34:59 +0100 | [diff] [blame] | 112 | u32 val = cpuid_eax(1); |
| 113 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
Kangheui Won | dad067f | 2021-05-06 15:53:37 +1000 | [diff] [blame] | 114 | |
| 115 | if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { |
| 116 | verify_psp_transfer_buf(); |
| 117 | show_psp_transfer_info(); |
| 118 | } |
| 119 | |
Felix Held | 153f92a | 2020-12-08 17:27:30 +0100 | [diff] [blame] | 120 | fch_early_init(); |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 121 | } |