Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Angel Pons | 2f30e8c | 2020-09-16 13:29:21 +0200 | [diff] [blame] | 5 | #include <southbridge/intel/i82801ix/i82801ix.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 6 | #include "gm45.h" |
| 7 | |
| 8 | void gm45_early_init(void) |
| 9 | { |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame] | 10 | const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 11 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 12 | /* Setup MCHBAR. */ |
Angel Pons | f462b3d | 2021-01-20 00:36:31 +0100 | [diff] [blame] | 13 | pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 14 | |
| 15 | /* Setup DMIBAR. */ |
Angel Pons | f462b3d | 2021-01-20 00:36:31 +0100 | [diff] [blame] | 16 | pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 17 | |
| 18 | /* Setup EPBAR. */ |
Angel Pons | f462b3d | 2021-01-20 00:36:31 +0100 | [diff] [blame] | 19 | pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | |
| 21 | pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); |
| 22 | |
| 23 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 24 | pci_write_config8(d0f0, D0F0_PAM(0), 0x30); |
| 25 | pci_write_config8(d0f0, D0F0_PAM(1), 0x33); |
| 26 | pci_write_config8(d0f0, D0F0_PAM(2), 0x33); |
| 27 | pci_write_config8(d0f0, D0F0_PAM(3), 0x33); |
| 28 | pci_write_config8(d0f0, D0F0_PAM(4), 0x33); |
| 29 | pci_write_config8(d0f0, D0F0_PAM(5), 0x33); |
| 30 | pci_write_config8(d0f0, D0F0_PAM(6), 0x33); |
| 31 | } |