Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: BSD-3-Clause |
| 2 | |
| 3 | # TODO: Move as much as possible to common |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 4 | # TODO: Update for Phoenix |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 5 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 6 | ifeq ($(CONFIG_SOC_AMD_PHOENIX),y) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 7 | |
| 8 | subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage |
| 9 | |
| 10 | # Beware that all-y also adds the compilation unit to verstage on PSP |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 11 | all-y += aoac.c |
Felix Held | 46cd1b5 | 2023-04-01 01:21:27 +0200 | [diff] [blame] | 12 | all-y += config.c |
| 13 | all-y += i2c.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 14 | |
Felix Held | f008e0a | 2023-04-01 01:31:24 +0200 | [diff] [blame] | 15 | # all_x86-y adds the compilation unit to all stages that run on the x86 cores |
| 16 | all_x86-y += gpio.c |
| 17 | all_x86-y += uart.c |
| 18 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 19 | bootblock-y += early_fch.c |
| 20 | bootblock-y += espi_util.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 21 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 22 | verstage-y += espi_util.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 23 | |
| 24 | romstage-y += fsp_m_params.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 25 | romstage-y += romstage.c |
Felix Held | 8f705b9 | 2023-02-06 19:56:35 +0100 | [diff] [blame] | 26 | romstage-y += soc_util.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 27 | |
| 28 | ramstage-y += acpi.c |
| 29 | ramstage-y += agesa_acpi.c |
| 30 | ramstage-y += chip.c |
| 31 | ramstage-y += cpu.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 32 | ramstage-y += fch.c |
| 33 | ramstage-y += fsp_s_params.c |
Ritul Guru | 4843ded | 2023-02-20 00:45:11 +0530 | [diff] [blame] | 34 | ramstage-y += graphics.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 35 | ramstage-y += mca.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 36 | ramstage-y += root_complex.c |
Felix Held | 8f705b9 | 2023-02-06 19:56:35 +0100 | [diff] [blame] | 37 | ramstage-y += soc_util.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 38 | ramstage-y += xhci.c |
| 39 | |
| 40 | smm-y += gpio.c |
| 41 | smm-y += smihandler.c |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 42 | smm-$(CONFIG_DEBUG_SMI) += uart.c |
| 43 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 44 | CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include |
| 45 | CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi |
| 46 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 47 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common |
| 48 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 49 | # ROMSIG Normally At ROMBASE + 0x20000 |
| 50 | # Overridden by CONFIG_AMD_FWM_POSITION_INDEX |
| 51 | # +-----------+---------------+----------------+------------+ |
| 52 | # |0x55AA55AA | | | | |
| 53 | # +-----------+---------------+----------------+------------+ |
| 54 | # | | PSPDIR ADDR | BIOSDIR ADDR | |
| 55 | # +-----------+---------------+----------------+ |
| 56 | |
| 57 | $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ |
| 58 | $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) |
| 59 | |
Martin Roth | b486fe9 | 2023-01-09 21:21:48 -0700 | [diff] [blame] | 60 | # Fixed EFS location |
| 61 | PHOENIX_FWM_POSITION=0xff020000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 62 | |
| 63 | # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes |
| 64 | # Building the cbfs image will fail if the offset isn't large enough |
| 65 | AMD_FW_AB_POSITION := 0x40 |
| 66 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 67 | PHOENIX_FW_A_POSITION=$(call int-add, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 68 | $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 69 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 70 | PHOENIX_FW_B_POSITION=$(call int-add, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 71 | $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 72 | # |
| 73 | # PSP Directory Table items |
| 74 | # |
| 75 | # Certain ordering requirements apply, however these are ensured by amdfwtool. |
| 76 | # For more information see "AMD Platform Security Processor BIOS Architecture |
| 77 | # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). |
| 78 | # |
| 79 | |
| 80 | ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) |
| 81 | PSP_SOFTFUSE_BITS += 7 |
| 82 | endif |
| 83 | |
| 84 | ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) |
| 85 | # Enable secure debug unlock |
| 86 | PSP_SOFTFUSE_BITS += 0 |
| 87 | OPT_TOKEN_UNLOCK="--token-unlock" |
| 88 | endif |
| 89 | |
| 90 | ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) |
| 91 | OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" |
| 92 | else |
| 93 | # Disable MP2 firmware loading |
| 94 | PSP_SOFTFUSE_BITS += 29 |
| 95 | endif |
| 96 | |
| 97 | # Use additional Soft Fuse bits specified in Kconfig |
| 98 | PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) |
| 99 | |
| 100 | # type = 0x3a |
| 101 | ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) |
| 102 | PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) |
| 103 | endif |
| 104 | |
| 105 | # type = 0x55 |
| 106 | ifeq ($(CONFIG_HAVE_SPL_FILE),y) |
| 107 | SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
| 108 | ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) |
| 109 | SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) |
| 110 | else |
| 111 | SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
| 112 | endif |
| 113 | endif |
| 114 | |
| 115 | # |
| 116 | # BIOS Directory Table items - proper ordering is managed by amdfwtool |
| 117 | # |
| 118 | |
| 119 | # type = 0x60 |
| 120 | PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) |
| 121 | |
| 122 | # type = 0x61 |
| 123 | PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) |
| 124 | |
| 125 | # type = 0x62 |
| 126 | PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img |
| 127 | PSP_ELF_FILE=$(objcbfs)/bootblock.elf |
Felix Held | 3b89c95 | 2022-11-22 20:02:46 +0100 | [diff] [blame] | 128 | PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') |
| 129 | PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 130 | |
| 131 | # type = 0x63 - construct APOB NV base/size from flash map |
| 132 | # The flashmap section used for this is expected to be named RW_MRC_CACHE |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 133 | APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) |
Fred Reitberger | 41a162b | 2023-06-29 12:58:53 -0400 | [diff] [blame^] | 134 | APOB_NV_BASE=$(shell printf "%#x" $(call int-subtract, \ |
| 135 | $(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) \ |
| 136 | $(call get_fmap_value,FMAP_SECTION_FLASH_START))) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 137 | |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 138 | ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) |
| 139 | # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. |
| 140 | # Else use RW_MRC_CACHE. This entry will be added in the RO section. |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 141 | APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) |
Fred Reitberger | 41a162b | 2023-06-29 12:58:53 -0400 | [diff] [blame^] | 142 | APOB_NV_RO_BASE=$(shell printf "%#x" $(call int-subtract, \ |
| 143 | $(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) \ |
| 144 | $(call get_fmap_value,FMAP_SECTION_FLASH_START))) |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 145 | else |
| 146 | APOB_NV_RO_SIZE=$(APOB_NV_SIZE) |
| 147 | APOB_NV_RO_BASE=$(APOB_NV_BASE) |
| 148 | endif |
| 149 | |
Zheng Bao | a4284b0 | 2023-02-01 13:16:52 +0800 | [diff] [blame] | 150 | ifeq ($(CONFIG_AMDFW_SPLIT),y) |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 151 | FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) |
Zheng Bao | a4284b0 | 2023-02-01 13:16:52 +0800 | [diff] [blame] | 152 | endif |
| 153 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 154 | ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) |
| 155 | # type = 0x6B - PSP Shared memory location |
| 156 | ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) |
| 157 | PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) |
| 158 | PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) |
| 159 | endif |
| 160 | |
| 161 | # type = 0x52 - PSP Bootloader Userspace Application (verstage) |
| 162 | PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) |
| 163 | PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) |
| 164 | endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 165 | |
| 166 | ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) |
| 167 | SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 168 | $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ |
| 169 | $(call get_fmap_value,FMAP_SECTION_FLASH_START)) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 170 | SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 171 | $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ |
| 172 | $(call get_fmap_value,FMAP_SECTION_FLASH_START)) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 173 | SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed |
| 174 | SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed |
| 175 | endif # CONFIG_SEPARATE_SIGNED_PSPFW |
| 176 | |
| 177 | # Helper function to return a value with given bit set |
| 178 | # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. |
| 179 | set-bit=$(call int-shift-left, 1 $(call _toint,$1)) |
| 180 | PSP_SOFTFUSE=$(shell A=$(call int-add, \ |
| 181 | $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) |
| 182 | |
| 183 | # |
| 184 | # Build the arguments to amdfwtool (order is unimportant). Missing file names |
| 185 | # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. |
| 186 | # |
| 187 | |
| 188 | add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) |
| 189 | |
| 190 | OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) |
| 191 | OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) |
| 192 | |
| 193 | OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ |
| 194 | $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ |
| 195 | $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) |
| 196 | |
| 197 | OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) |
| 198 | OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) |
| 199 | OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) |
| 200 | OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) |
| 201 | |
| 202 | OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) |
| 203 | OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) |
| 204 | OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) |
| 205 | OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 206 | OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) |
| 207 | OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 208 | OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) |
| 209 | OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) |
| 210 | OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) |
| 211 | |
| 212 | OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) |
| 213 | OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) |
| 214 | OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) |
| 215 | OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) |
| 216 | |
| 217 | OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) |
| 218 | |
| 219 | OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) |
| 220 | OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) |
| 221 | OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) |
| 222 | |
| 223 | # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant |
| 224 | OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) |
| 225 | |
Zheng Bao | a4284b0 | 2023-02-01 13:16:52 +0800 | [diff] [blame] | 226 | OPT_AMDFW_BODY_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_LOCATION), --body-location) |
| 227 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 228 | AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ |
| 229 | $(OPT_APOB_ADDR) \ |
Martin Roth | 0acf59d | 2023-03-08 15:18:24 -0700 | [diff] [blame] | 230 | $(OPT_DEBUG_AMDFWTOOL) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 231 | $(OPT_PSP_BIOSBIN_FILE) \ |
| 232 | $(OPT_PSP_BIOSBIN_DEST) \ |
| 233 | $(OPT_PSP_BIOSBIN_SIZE) \ |
| 234 | $(OPT_PSP_SOFTFUSE) \ |
| 235 | $(OPT_PSP_LOAD_MP2_FW) \ |
| 236 | --use-pspsecureos \ |
| 237 | --load-s0i3 \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 238 | $(OPT_TOKEN_UNLOCK) \ |
| 239 | $(OPT_WHITELIST_FILE) \ |
| 240 | $(OPT_PSP_SHAREDMEM_BASE) \ |
| 241 | $(OPT_PSP_SHAREDMEM_SIZE) \ |
| 242 | $(OPT_EFS_SPI_READ_MODE) \ |
| 243 | $(OPT_EFS_SPI_SPEED) \ |
| 244 | $(OPT_EFS_SPI_MICRON_FLAG) \ |
| 245 | --config $(CONFIG_AMDFW_CONFIG_FILE) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 246 | --flashsize $(CONFIG_ROM_SIZE) \ |
Zheng Bao | a4284b0 | 2023-02-01 13:16:52 +0800 | [diff] [blame] | 247 | $(OPT_RECOVERY_AB_SINGLE_COPY) \ |
| 248 | $(OPT_AMDFW_BODY_LOCATION) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 249 | |
| 250 | $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ |
| 251 | $(PSP_VERSTAGE_FILE) \ |
| 252 | $(PSP_VERSTAGE_SIG_FILE) \ |
| 253 | $$(PSP_APCB_FILES) \ |
| 254 | $(DEP_FILES) \ |
| 255 | $(AMDFWTOOL) \ |
| 256 | $(obj)/fmap_config.h \ |
| 257 | $(objcbfs)/bootblock.elf # this target also creates the .map file |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 258 | rm -f $@ |
| 259 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 260 | $(AMDFWTOOL) \ |
| 261 | $(AMDFW_COMMON_ARGS) \ |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 262 | $(OPT_APOB_NV_RO_SIZE) \ |
| 263 | $(OPT_APOB_NV_RO_BASE) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 264 | $(OPT_VERSTAGE_FILE) \ |
| 265 | $(OPT_VERSTAGE_SIG_FILE) \ |
| 266 | $(OPT_SPL_TABLE_FILE) \ |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 267 | --location $(shell printf "%#x" $(PHOENIX_FWM_POSITION)) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 268 | --output $@ |
| 269 | |
Zheng Bao | a4284b0 | 2023-02-01 13:16:52 +0800 | [diff] [blame] | 270 | ifeq ($(CONFIG_AMDFW_SPLIT),y) |
| 271 | $(obj)/amdfw.rom.body: $(obj)/amdfw.rom |
| 272 | $(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body) |
| 273 | $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward |
| 274 | endif |
| 275 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 276 | $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) |
| 277 | rm -f $@ |
| 278 | @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" |
| 279 | $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ |
| 280 | --maxsize $(PSP_BIOSBIN_SIZE) |
| 281 | |
| 282 | $(obj)/amdfw_a.rom: $(obj)/amdfw.rom |
| 283 | rm -f $@ |
| 284 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 285 | $(AMDFWTOOL) \ |
| 286 | $(AMDFW_COMMON_ARGS) \ |
| 287 | $(OPT_APOB_NV_SIZE) \ |
| 288 | $(OPT_APOB_NV_BASE) \ |
| 289 | $(OPT_SPL_RW_AB_TABLE_FILE) \ |
| 290 | $(OPT_SIGNED_AMDFW_A_POSITION) \ |
| 291 | $(OPT_SIGNED_AMDFW_A_FILE) \ |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 292 | --location $(shell printf "%#x" $(PHOENIX_FW_A_POSITION)) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 293 | --anywhere \ |
| 294 | --output $@ |
| 295 | |
| 296 | $(obj)/amdfw_b.rom: $(obj)/amdfw.rom |
| 297 | rm -f $@ |
| 298 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 299 | $(AMDFWTOOL) \ |
| 300 | $(AMDFW_COMMON_ARGS) \ |
| 301 | $(OPT_APOB_NV_SIZE) \ |
| 302 | $(OPT_APOB_NV_BASE) \ |
| 303 | $(OPT_SPL_RW_AB_TABLE_FILE) \ |
| 304 | $(OPT_SIGNED_AMDFW_B_POSITION) \ |
| 305 | $(OPT_SIGNED_AMDFW_B_FILE) \ |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 306 | --location $(shell printf "%#x" $(PHOENIX_FW_B_POSITION)) \ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 307 | --anywhere \ |
| 308 | --output $@ |
| 309 | |
| 310 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 311 | ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) |
| 312 | cbfs-files-y += apu/amdfw_a |
| 313 | apu/amdfw_a-file := $(obj)/amdfw_a.rom |
| 314 | apu/amdfw_a-position := $(AMD_FW_AB_POSITION) |
| 315 | apu/amdfw_a-type := raw |
| 316 | |
| 317 | cbfs-files-y += apu/amdfw_b |
| 318 | apu/amdfw_b-file := $(obj)/amdfw_b.rom |
| 319 | apu/amdfw_b-position := $(AMD_FW_AB_POSITION) |
| 320 | apu/amdfw_b-type := raw |
| 321 | |
| 322 | ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) |
| 323 | build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom |
| 324 | @printf " Adding Signed ROM and HASH\n" |
| 325 | $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed |
| 326 | $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed |
| 327 | $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ |
| 328 | -n apu/amdfw_a_hash -t raw |
| 329 | $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ |
| 330 | -n apu/amdfw_b_hash -t raw |
| 331 | endif # CONFIG_SEPARATE_SIGNED_PSPFW |
| 332 | endif |
| 333 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 334 | endif # ($(CONFIG_SOC_AMD_PHOENIX),y) |