Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 40f558e8f4f77ab70a8a2eb9bdfa850e362cb553 / . / src / soc / rockchip / rk3288 / vop.c
blob: 378e6b8e90325885b93cd6dae674a8777dfcd24d [file] [log] [blame]
huang lin40f558e2014-09-19 14:51:52 +0800[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <arch/io.h>
21#include <console/console.h>
22#include <delay.h>
23#include <stdlib.h>
24#include <string.h>
25#include <stddef.h>
26#include <soc/addressmap.h>
27#include <soc/clock.h>
28#include <soc/edp.h>
29#include <soc/vop.h>
30
31#include "chip.h"
32
33static struct rk3288_vop_regs * const vop_regs[] = {
34 (struct rk3288_vop_regs *)VOP_BIG_BASE,
35 (struct rk3288_vop_regs *)VOP_LIT_BASE
36};
37
38void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
39{
40 u32 lb_mode;
41 u32 rgb_mode;
42 u32 hactive = edid->ha;
43 u32 vactive = edid->va;
44 u32 hsync_len = edid->hspw;
45 u32 hback_porch = edid->hbl - edid->hso - edid->hspw;
46 u32 vsync_len = edid->vspw;
47 u32 vback_porch = edid->vbl - edid->vso - edid->vspw;
48 u32 xpos = 0, ypos = 0;
49 struct rk3288_vop_regs *preg = vop_regs[vop_id];
50
51 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
52 &preg->win0_act_info);
53
54 writel(V_DSP_XST(xpos + hsync_len + hback_porch) |
55 V_DSP_YST(ypos + vsync_len + vback_porch),
56 &preg->win0_dsp_st);
57
58 writel(V_DSP_WIDTH(hactive - 1) |
59 V_DSP_HEIGHT(vactive - 1),
60 &preg->win0_dsp_info);
61
62 clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
63 V_WIN0_KEY_EN(0) |
64 V_WIN0_KEY_COLOR(0));
65
66 switch (edid->framebuffer_bits_per_pixel) {
67 case 16:
68 rgb_mode = RGB565;
69 writel(V_RGB565_VIRWIDTH(hactive),
70 &preg->win0_vir);
71 break;
72 case 24:
73 rgb_mode = RGB888;
74 writel(V_RGB888_VIRWIDTH(hactive),
75 &preg->win0_vir);
76 break;
77 case 32:
78 default:
79 rgb_mode = ARGB8888;
80 writel(V_ARGB888_VIRWIDTH(hactive),
81 &preg->win0_vir);
82 break;
83 }
84
85 if (hactive > 2560)
86 lb_mode = LB_RGB_3840X2;
87 else if (hactive > 1920)
88 lb_mode = LB_RGB_2560X4;
89 else if (hactive > 1280)
90 lb_mode = LB_RGB_1920X5;
91 else
92 lb_mode = LB_RGB_1280X8;
93
94 clrsetbits_le32(&preg->win0_ctrl0,
95 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
96 V_WIN0_LB_MODE(lb_mode) |
97 V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
98
99 writel(fbbase, &preg->win0_yrgb_mst);
100
101 writel(0x01, &preg->reg_cfg_done); /* enable reg config */
102}
103
104void rkvop_mode_set(u32 vop_id, const struct edid *edid)
105{
106 u32 hactive = edid->ha;
107 u32 vactive = edid->va;
108 u32 hfront_porch = edid->hso;
109 u32 hsync_len = edid->hspw;
110 u32 hback_porch = edid->hbl - edid->hso - edid->hspw;
111 u32 vfront_porch = edid->vso;
112 u32 vsync_len = edid->vspw;
113 u32 vback_porch = edid->vbl - edid->vso - edid->vspw;
114 struct rk3288_vop_regs *preg = vop_regs[vop_id];
115
116 clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1));
117 clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE,
118 V_DSP_OUT_MODE(15));
119 writel(V_HSYNC(hsync_len) |
120 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
121 &preg->dsp_htotal_hs_end);
122
123 writel(V_HEAP(hsync_len + hback_porch + hactive) |
124 V_HASP(hsync_len + hback_porch),
125 &preg->dsp_hact_st_end);
126
127 writel(V_VSYNC(vsync_len) |
128 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
129 &preg->dsp_vtotal_vs_end);
130
131 writel(V_VAEP(vsync_len + vback_porch + vactive)|
132 V_VASP(vsync_len + vback_porch),
133 &preg->dsp_vact_st_end);
134
135 writel(V_HEAP(hsync_len + hback_porch + hactive) |
136 V_HASP(hsync_len + hback_porch),
137 &preg->post_dsp_hact_info);
138
139 writel(V_VAEP(vsync_len + vback_porch + vactive)|
140 V_VASP(vsync_len + vback_porch),
141 &preg->post_dsp_vact_info);
142
143 writel(0x01, &preg->reg_cfg_done); /* enable reg config */
144}