Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Martin Roth | 726504a | 2020-10-30 16:41:32 -0600 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 4 | #include <baseboard/variants.h> |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 5 | #include <delay.h> |
Martin Roth | 726504a | 2020-10-30 16:41:32 -0600 | [diff] [blame] | 6 | #include <ec/google/chromeec/ec.h> |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 7 | #include <gpio.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 8 | #include <soc/smi.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 9 | #include <variant/gpio.h> |
| 10 | |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 11 | static const struct soc_amd_gpio gpio_set_stage_ram[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 12 | /* PWR_BTN_L */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 13 | PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 14 | /* SYS_RESET_L */ |
| 15 | PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), |
Rob Barnes | d1095c7 | 2020-09-25 14:16:46 -0600 | [diff] [blame] | 16 | /* WIFI_PCIE_WAKE_ODL */ |
Felix Held | f8e440c | 2021-03-24 00:17:35 +0100 | [diff] [blame] | 17 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 18 | /* H1_FCH_INT_ODL */ |
| 19 | PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 20 | /* PEN_DETECT_ODL */ |
Furquan Shaikh | 16868bc | 2020-06-30 16:13:47 -0700 | [diff] [blame] | 21 | PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 22 | /* PEN_POWER_EN - Enabled*/ |
| 23 | PAD_GPO(GPIO_5, HIGH), |
| 24 | /* FPMCU_INT_L */ |
Furquan Shaikh | b0334e1 | 2020-09-11 15:43:45 -0700 | [diff] [blame] | 25 | PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 26 | /* I2S_SDIN */ |
| 27 | PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), |
| 28 | /* I2S_LRCLK - Bit banged in depthcharge */ |
| 29 | PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), |
| 30 | /* TOUCHPAD_INT_ODL */ |
Victor Ding | c82db71 | 2021-04-15 04:31:54 +0000 | [diff] [blame] | 31 | PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), |
Martin Roth | 6a62cc8 | 2020-12-02 16:37:58 -0700 | [diff] [blame] | 32 | /* S0iX SLP - goes to EC & FPMCU */ |
| 33 | PAD_GPO(GPIO_10, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 34 | /* USI_INT_ODL */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 35 | PAD_GPI(GPIO_12, PULL_NONE), |
Furquan Shaikh | da459c4 | 2020-06-18 01:34:48 -0700 | [diff] [blame] | 36 | /* EN_PWR_TOUCHPAD_PS2 */ |
| 37 | PAD_GPO(GPIO_13, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 38 | /* BT_DISABLE */ |
| 39 | PAD_GPO(GPIO_14, LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 40 | /* GPIO_15: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 41 | /* USB_OC0_L - USB C0 + USB A0 */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 42 | PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 43 | /* USB_OC1_L - USB C1 + USB A1 */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 44 | PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 45 | /* WIFI_DISABLE */ |
| 46 | PAD_GPO(GPIO_18, LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 47 | /* I2C3_SCL - H1 */ |
| 48 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 49 | /* I2C3_SDA - H1 */ |
| 50 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 51 | /* EMMC_CMD */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 52 | PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 53 | /* EC_FCH_SCI_ODL */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 54 | PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 55 | /* AC_PRES */ |
| 56 | PAD_NF(GPIO_23, AC_PRES, PULL_UP), |
Furquan Shaikh | 489ffef | 2020-06-30 14:08:27 -0700 | [diff] [blame] | 57 | /* EC_FCH_WAKE_L */ |
| 58 | PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 59 | /* GPIO_25: Not available */ |
| 60 | /* PCIE_RST0_L - Fixed timings */ |
| 61 | PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), |
| 62 | /* PCIE_RST1_L (unused) */ |
| 63 | PAD_NC(GPIO_27), |
| 64 | /* GPIO_28: Not available */ |
Josie Nordrum | cc72e15 | 2020-08-03 11:39:41 -0600 | [diff] [blame] | 65 | /* GPIO_29: HP_INT_ODL */ |
| 66 | PAD_GPI(GPIO_29, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 67 | /* FCH_ESPI_EC_CS_L */ |
| 68 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 69 | /* EC_AP_INT_ODL (Sensor Framesync) */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 70 | PAD_GPI(GPIO_31, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 71 | /* GPIO_33 - GPIO_39: Not available */ |
| 72 | /* NVME_AUX_RESET_L */ |
| 73 | PAD_GPO(GPIO_40, HIGH), |
| 74 | /* GPIO_41: Not available */ |
| 75 | /* GPIO_42: Handled in bootblock for wifi power/reset control. */ |
| 76 | /* GPIO_43 - GPIO_66: Not available */ |
Furquan Shaikh | da459c4 | 2020-06-18 01:34:48 -0700 | [diff] [blame] | 77 | /* DMIC SEL */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 78 | /* |
Furquan Shaikh | da459c4 | 2020-06-18 01:34:48 -0700 | [diff] [blame] | 79 | * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash |
| 80 | * access will be very slow. |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 81 | */ |
Furquan Shaikh | da459c4 | 2020-06-18 01:34:48 -0700 | [diff] [blame] | 82 | PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic |
Kevin Chiu | 768f59a | 2020-09-26 20:34:28 +0800 | [diff] [blame] | 83 | /* EMMC_RESET_L */ |
| 84 | PAD_GPO(GPIO_68, HIGH), |
Martin Roth | 726504a | 2020-10-30 16:41:32 -0600 | [diff] [blame] | 85 | /* FPMCU_BOOT0 */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 86 | PAD_GPO(GPIO_69, LOW), |
| 87 | /* EMMC_CLK */ |
| 88 | PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 89 | /* GPIO_71 - GPIO_73: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 90 | /* EMMC_DATA4 */ |
| 91 | PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), |
| 92 | /* EMMC_DATA6 */ |
| 93 | PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), |
| 94 | /* EN_PWR_CAMERA */ |
| 95 | PAD_GPO(GPIO_76, HIGH), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 96 | /* GPIO_77 - GPIO_83: Not available */ |
| 97 | /* RAM_ID_4 */ |
| 98 | PAD_GPI(GPIO_84, PULL_NONE), |
Chris Wang | ad481c4 | 2020-12-01 17:14:17 +0800 | [diff] [blame] | 99 | /* APU_EDP_BL_DISABLE */ |
| 100 | PAD_GPO(GPIO_85, LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 101 | /* WIFI_AUX_RESET_L */ |
| 102 | PAD_GPO(GPIO_86, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 103 | /* EMMC_DATA7 */ |
| 104 | PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), |
| 105 | /* EMMC_DATA5 */ |
| 106 | PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), |
Furquan Shaikh | 79dba4a | 2020-08-04 17:16:33 -0700 | [diff] [blame] | 107 | /* GPIO_89 - unused */ |
| 108 | PAD_NC(GPIO_89), |
Furquan Shaikh | 5474f8e | 2020-08-05 14:54:39 -0700 | [diff] [blame] | 109 | /* EN_PWR_TOUCHSCREEN */ |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 110 | PAD_GPO(GPIO_90, HIGH), |
Furquan Shaikh | 7f892b5 | 2020-07-21 22:54:16 -0700 | [diff] [blame] | 111 | /* EN_SPKR */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 112 | PAD_GPO(GPIO_91, LOW), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 113 | /* CLK_REQ0_L - WIFI */ |
| 114 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
| 115 | /* GPIO_93 - GPIO_103: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 116 | /* EMMC_DATA0 */ |
| 117 | PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), |
| 118 | /* EMMC_DATA1 */ |
| 119 | PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), |
| 120 | /* EMMC_DATA2 */ |
| 121 | PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), |
| 122 | /* EMMC_DATA3 */ |
| 123 | PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 124 | /* ESPI_ALERT_L */ |
| 125 | PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 126 | /* EMMC_DS */ |
| 127 | PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 128 | /* GPIO_110 - GPIO112: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 129 | /* I2C2_SCL - USI/Touchpad */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 130 | PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 131 | /* I2C2_SDA - USI/Touchpad */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 132 | PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 133 | /* CLK_REQ1_L - SD Card */ |
| 134 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
| 135 | /* RAM_ID_3 */ |
| 136 | PAD_GPI(GPIO_116, PULL_NONE), |
| 137 | /* GPIO_117 - GPIO_119: Not available */ |
| 138 | /* RAM_ID_1 */ |
| 139 | PAD_GPI(GPIO_120, PULL_NONE), |
| 140 | /* RAM_ID_0 */ |
| 141 | PAD_GPI(GPIO_121, PULL_NONE), |
| 142 | /* GPIO_122 - GPIO_128: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 143 | /* KBRST_L */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 144 | PAD_NF(GPIO_129, KBRST_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 145 | /* EC_IN_RW_OD */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 146 | PAD_GPI(GPIO_130, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 147 | /* RAM_ID_2 */ |
| 148 | PAD_GPI(GPIO_131, PULL_NONE), |
| 149 | /* CLK_REQ4_L - SSD */ |
| 150 | PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), |
| 151 | /* GPIO_133 - GPIO_134: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 152 | /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ |
| 153 | PAD_GPI(GPIO_135, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 154 | /* UART0_RXD - DEBUG */ |
| 155 | PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), |
Furquan Shaikh | ca36acf | 2020-07-03 10:32:41 -0700 | [diff] [blame] | 156 | /* BIOS_FLASH_WP_ODL */ |
| 157 | PAD_GPI(GPIO_137, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 158 | /* UART0_TXD - DEBUG */ |
| 159 | PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 160 | /* DEV_BEEP_BCLK */ |
| 161 | PAD_GPI(GPIO_139, PULL_NONE), |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 162 | /* TOUCHSCREEN_RESET_L */ |
| 163 | PAD_GPO(GPIO_140, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 164 | /* UART1_RXD - FPMCU */ |
| 165 | PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), |
Furquan Shaikh | 65e1117 | 2020-07-21 21:51:27 -0700 | [diff] [blame] | 166 | /* SD_AUX_RESET_L */ |
| 167 | PAD_GPO(GPIO_142, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 168 | /* UART1_TXD - FPMCU */ |
| 169 | PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), |
| 170 | /* USI_REPORT_EN */ |
Furquan Shaikh | dcee4b6 | 2020-07-22 00:47:40 -0700 | [diff] [blame] | 171 | PAD_GPO(GPIO_144, LOW), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 172 | }; |
| 173 | |
Matt DeVillier | 4a16be9 | 2022-09-23 13:36:36 -0500 | [diff] [blame] | 174 | const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 175 | { |
| 176 | *size = ARRAY_SIZE(gpio_set_stage_ram); |
| 177 | return gpio_set_stage_ram; |
| 178 | } |
| 179 | |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 180 | static void wifi_power_reset_configure_active_low_power(void) |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 181 | { |
| 182 | /* |
| 183 | * Configure WiFi GPIOs such that: |
| 184 | * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 185 | * - Enable power to WiFi using EN_PWR_WIFI_L. |
Martin Roth | cdd7d18 | 2020-11-18 09:20:01 -0700 | [diff] [blame] | 186 | * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) |
| 187 | * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 188 | */ |
| 189 | static const struct soc_amd_gpio v3_wifi_table[] = { |
| 190 | /* WIFI_AUX_RESET_L */ |
| 191 | PAD_GPO(GPIO_86, LOW), |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 192 | /* EN_PWR_WIFI_L */ |
| 193 | PAD_GPO(GPIO_42, LOW), |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 194 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 195 | gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 196 | |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 197 | } |
| 198 | |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 199 | static void wifi_power_reset_configure_active_high_power(void) |
| 200 | { |
| 201 | /* |
| 202 | * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L |
| 203 | * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be |
| 204 | * set low before driving it high to trigger a WiFi power cycle to meet PCIe |
| 205 | * requirements. Thus, configura GPIOs such that: |
| 206 | * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device |
| 207 | * - Disable power to WiFi. |
| 208 | * - Wait 10ms for WiFi power to go low. |
| 209 | * - Enable power to WiFi using EN_PWR_WIFI. |
| 210 | * - Deassert WIFI_AUX_RESET_L. |
| 211 | */ |
| 212 | static const struct soc_amd_gpio v3_wifi_table[] = { |
| 213 | /* WIFI_AUX_RESET_L */ |
| 214 | PAD_GPO(GPIO_86, LOW), |
| 215 | /* EN_PWR_WIFI */ |
| 216 | PAD_GPO(GPIO_42, LOW), |
| 217 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 218 | gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 219 | |
| 220 | mdelay(10); |
| 221 | gpio_set(GPIO_42, 1); |
| 222 | mdelay(50); |
| 223 | gpio_set(GPIO_86, 1); |
| 224 | } |
| 225 | |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 226 | static void wifi_power_reset_configure_v3(void) |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 227 | { |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 228 | if (variant_has_active_low_wifi_power()) |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 229 | wifi_power_reset_configure_active_low_power(); |
| 230 | else |
| 231 | wifi_power_reset_configure_active_high_power(); |
| 232 | } |
| 233 | |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 234 | static void wifi_power_reset_configure_pre_v3(void) |
| 235 | { |
| 236 | /* |
| 237 | * Configure WiFi GPIOs such that: |
| 238 | * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. |
| 239 | * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# |
| 240 | * deassertion causing WiFi to enter a bad state. |
| 241 | * - Wait 10ms for WiFi power to go low. |
| 242 | * - Enable power to WiFi using EN_PWR_WIFI. |
| 243 | * - Wait for 50ms after power to WiFi is enabled. |
| 244 | * - Deassert WIFI_AUX_RESET_L. |
| 245 | */ |
| 246 | static const struct soc_amd_gpio pre_v3_wifi_table[] = { |
| 247 | /* WIFI_AUX_RESET_L */ |
| 248 | PAD_GPO(GPIO_42, LOW), |
| 249 | /* EN_PWR_WIFI */ |
| 250 | PAD_GPO(GPIO_29, LOW), |
| 251 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 252 | gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 253 | |
| 254 | mdelay(10); |
| 255 | gpio_set(GPIO_29, 1); |
| 256 | mdelay(50); |
| 257 | gpio_set(GPIO_42, 1); |
| 258 | } |
| 259 | |
Matt DeVillier | bfad0b0 | 2022-11-11 10:56:07 -0600 | [diff] [blame] | 260 | void baseboard_pcie_gpio_configure(void) |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 261 | { |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 262 | static const struct soc_amd_gpio pcie_gpio_table[] = { |
| 263 | /* NVME_AUX_RESET_L */ |
| 264 | PAD_GPO(GPIO_40, HIGH), |
| 265 | /* CLK_REQ0_L - WIFI */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 266 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 267 | /* CLK_REQ1_L - SD Card */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 268 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 269 | /* CLK_REQ4_L - SSD */ |
Furquan Shaikh | 7571110d | 2020-07-16 11:26:10 -0700 | [diff] [blame] | 270 | PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 271 | /* SD_AUX_RESET_L */ |
| 272 | PAD_GPO(GPIO_142, HIGH), |
| 273 | }; |
| 274 | |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 275 | gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 276 | |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 277 | if (variant_uses_v3_schematics()) |
| 278 | wifi_power_reset_configure_v3(); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 279 | else |
| 280 | wifi_power_reset_configure_pre_v3(); |
| 281 | } |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 282 | |
Martin Roth | 726504a | 2020-10-30 16:41:32 -0600 | [diff] [blame] | 283 | __weak void finalize_gpios(int slp_typ) |
| 284 | { |
| 285 | if (variant_has_fingerprint() && slp_typ != ACPI_S3) { |
| 286 | |
| 287 | if (fpmcu_needs_delay()) |
| 288 | mdelay(550); |
| 289 | |
| 290 | /* |
| 291 | * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out |
| 292 | * of reset by setting FPMCU_RST_L high 3ms later. |
| 293 | */ |
| 294 | gpio_set(GPIO_32, 1); |
| 295 | mdelay(3); |
| 296 | gpio_set(GPIO_11, 1); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { |
| 301 | /* FPMCU_RST_L */ |
| 302 | PAD_GPO(GPIO_11, LOW), |
| 303 | /* EN_PWR_FP */ |
| 304 | PAD_GPO(GPIO_32, LOW), |
| 305 | }; |
| 306 | |
| 307 | static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { |
| 308 | /* FPMCU_RST_L */ |
| 309 | PAD_NC(GPIO_11), |
| 310 | /* EN_PWR_FP */ |
| 311 | PAD_NC(GPIO_32), |
| 312 | }; |
| 313 | |
| 314 | const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) |
| 315 | { |
| 316 | if (variant_has_fingerprint()) { |
| 317 | if (slp_typ == ACPI_S3) |
| 318 | return NULL; |
| 319 | |
| 320 | *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); |
| 321 | return gpio_fingerprint_bootblock_table; |
| 322 | } |
| 323 | |
| 324 | *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); |
| 325 | return gpio_no_fingerprint_bootblock_table; |
| 326 | } |
| 327 | |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 328 | static const struct soc_amd_gpio gpio_sleep_table[] = { |
Martin Roth | 6a62cc8 | 2020-12-02 16:37:58 -0700 | [diff] [blame] | 329 | /* S0iX SLP */ |
| 330 | PAD_GPO(GPIO_10, LOW), |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 331 | /* NVME_AUX_RESET_L */ |
| 332 | PAD_GPO(GPIO_40, LOW), |
| 333 | /* EN_PWR_CAMERA */ |
| 334 | PAD_GPO(GPIO_76, LOW), |
| 335 | }; |
| 336 | |
Martin Roth | d5c3d9c | 2020-10-30 16:43:31 -0600 | [diff] [blame] | 337 | static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { |
| 338 | /* NVME_AUX_RESET_L */ |
| 339 | PAD_GPO(GPIO_40, LOW), |
| 340 | /* EN_PWR_CAMERA */ |
| 341 | PAD_GPO(GPIO_76, LOW), |
| 342 | |
| 343 | /* FPMCU_RST_L */ |
| 344 | PAD_GPO(GPIO_11, LOW), |
| 345 | /* EN_PWR_FP */ |
| 346 | PAD_GPO(GPIO_32, LOW), |
| 347 | }; |
| 348 | |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 349 | const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) |
| 350 | { |
Martin Roth | d5c3d9c | 2020-10-30 16:43:31 -0600 | [diff] [blame] | 351 | if (slp_typ == SLP_TYP_S5) { |
| 352 | *size = ARRAY_SIZE(gpio_fp_shutdown_table); |
| 353 | return gpio_fp_shutdown_table; |
| 354 | } |
| 355 | |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 356 | *size = ARRAY_SIZE(gpio_sleep_table); |
| 357 | return gpio_sleep_table; |
| 358 | } |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 359 | |
Raul E Rangel | 04cf427 | 2021-12-06 12:15:45 -0700 | [diff] [blame] | 360 | static const struct soc_amd_gpio espi_gpio_table[] = { |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 361 | /* PCIE_RST0_L - Fixed timings */ |
| 362 | PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), |
| 363 | /* FCH_ESPI_EC_CS_L */ |
| 364 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
| 365 | /* ESPI_ALERT_L */ |
| 366 | PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), |
Raul E Rangel | 04cf427 | 2021-12-06 12:15:45 -0700 | [diff] [blame] | 367 | }; |
| 368 | |
| 369 | const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) |
| 370 | { |
| 371 | *size = ARRAY_SIZE(espi_gpio_table); |
| 372 | return espi_gpio_table; |
| 373 | } |
| 374 | |
| 375 | static const struct soc_amd_gpio tpm_gpio_table[] = { |
| 376 | /* H1_FCH_INT_ODL */ |
| 377 | PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), |
| 378 | /* I2C3_SCL - H1 */ |
| 379 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 380 | /* I2C3_SDA - H1 */ |
| 381 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
| 382 | /* EC_IN_RW_OD */ |
| 383 | PAD_GPI(GPIO_130, PULL_NONE), |
| 384 | }; |
| 385 | |
| 386 | const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) |
| 387 | { |
| 388 | *size = ARRAY_SIZE(tpm_gpio_table); |
| 389 | return tpm_gpio_table; |
| 390 | } |
| 391 | |
| 392 | static const struct soc_amd_gpio early_gpio_table[] = { |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 393 | /* UART0_RXD - DEBUG */ |
| 394 | PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), |
| 395 | /* UART0_TXD - DEBUG */ |
| 396 | PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 397 | }; |
| 398 | |
| 399 | const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) |
| 400 | { |
| 401 | *size = ARRAY_SIZE(early_gpio_table); |
| 402 | return early_gpio_table; |
| 403 | } |
Matt DeVillier | c429ee1 | 2022-11-11 16:14:33 -0600 | [diff] [blame] | 404 | |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 405 | static const struct soc_amd_gpio romstage_gpio_table[] = { |
| 406 | /* Enable touchscreen, hold in reset */ |
| 407 | /* EN_PWR_TOUCHSCREEN */ |
| 408 | PAD_GPO(GPIO_32, HIGH), |
| 409 | /* TOUCHSCREEN_RESET_L */ |
| 410 | PAD_GPO(GPIO_140, LOW), |
| 411 | }; |
Matt DeVillier | c429ee1 | 2022-11-11 16:14:33 -0600 | [diff] [blame] | 412 | |
| 413 | const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) |
| 414 | { |
| 415 | *size = ARRAY_SIZE(romstage_gpio_table); |
| 416 | return romstage_gpio_table; |
| 417 | } |