Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
Felix Held | 6593192 | 2021-04-15 00:14:12 +0200 | [diff] [blame] | 5 | #include <platform_descriptors.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 6 | #include <soc/soc_util.h> |
| 7 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 8 | void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, |
| 9 | size_t *dxio_num, |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 10 | const fsp_ddi_descriptor **ddi_descs, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 11 | size_t *ddi_num) |
| 12 | { |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 13 | *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 14 | *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); |
| 15 | } |
| 16 | |
| 17 | /* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some |
| 18 | * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. |
| 19 | * Those parts need to be configured as Type 2. */ |
| 20 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 21 | static const fsp_dxio_descriptor pco_dxio_descriptors[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 22 | { |
| 23 | // NVME SSD |
| 24 | .port_present = true, |
| 25 | .engine_type = PCIE_ENGINE, |
Felix Held | a19d986 | 2020-07-20 15:46:56 +0200 | [diff] [blame] | 26 | .start_logical_lane = 0, |
| 27 | .end_logical_lane = 3, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 28 | .device_number = 1, |
| 29 | .function_number = 7, |
| 30 | .link_aspm = ASPM_L1, |
| 31 | .link_aspm_L1_1 = true, |
| 32 | .link_aspm_L1_2 = true, |
| 33 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 34 | .clk_req = CLK_REQ4, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 35 | }, |
| 36 | { |
| 37 | // WLAN |
| 38 | .port_present = true, |
| 39 | .engine_type = PCIE_ENGINE, |
Felix Held | a19d986 | 2020-07-20 15:46:56 +0200 | [diff] [blame] | 40 | .start_logical_lane = 4, |
| 41 | .end_logical_lane = 4, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 42 | .device_number = 1, |
| 43 | .function_number = 2, |
| 44 | .link_aspm = ASPM_L1, |
| 45 | .link_aspm_L1_1 = true, |
| 46 | .link_aspm_L1_2 = true, |
| 47 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 48 | .clk_req = CLK_REQ0, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 49 | }, |
| 50 | { |
| 51 | // SD Reader |
| 52 | .port_present = true, |
| 53 | .engine_type = PCIE_ENGINE, |
Felix Held | a19d986 | 2020-07-20 15:46:56 +0200 | [diff] [blame] | 54 | .start_logical_lane = 5, |
| 55 | .end_logical_lane = 5, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 56 | .device_number = 1, |
| 57 | .function_number = 3, |
| 58 | .link_aspm = ASPM_L1, |
| 59 | .link_aspm_L1_1 = true, |
| 60 | .link_aspm_L1_2 = true, |
| 61 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 62 | .clk_req = CLK_REQ1, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 63 | } |
| 64 | }; |
| 65 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 66 | static const fsp_dxio_descriptor dali_dxio_descriptors[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 67 | { |
| 68 | // NVME SSD |
| 69 | .port_present = true, |
| 70 | .engine_type = PCIE_ENGINE, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 71 | .start_logical_lane = 0, |
| 72 | .end_logical_lane = 1, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 73 | .device_number = 1, |
| 74 | .function_number = 7, |
| 75 | .link_aspm = ASPM_L1, |
| 76 | .link_aspm_L1_1 = true, |
| 77 | .link_aspm_L1_2 = true, |
| 78 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 79 | .clk_req = CLK_REQ4, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 80 | }, |
| 81 | { |
| 82 | // WLAN |
| 83 | .port_present = true, |
| 84 | .engine_type = PCIE_ENGINE, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 85 | .start_logical_lane = 4, |
| 86 | .end_logical_lane = 4, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 87 | .device_number = 1, |
| 88 | .function_number = 2, |
| 89 | .link_aspm = ASPM_L1, |
| 90 | .link_aspm_L1_1 = true, |
| 91 | .link_aspm_L1_2 = true, |
| 92 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 93 | .clk_req = CLK_REQ0, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 94 | }, |
| 95 | { |
| 96 | // SD Reader |
| 97 | .port_present = true, |
| 98 | .engine_type = PCIE_ENGINE, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 99 | .start_logical_lane = 5, |
| 100 | .end_logical_lane = 5, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 101 | .device_number = 1, |
| 102 | .function_number = 3, |
| 103 | .link_aspm = ASPM_L1, |
| 104 | .link_aspm_L1_1 = true, |
| 105 | .link_aspm_L1_2 = true, |
| 106 | .turn_off_unused_lanes = true, |
Aaron Durbin | 80e2dd8 | 2020-07-29 13:54:22 -0600 | [diff] [blame] | 107 | .clk_req = CLK_REQ1, |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 108 | } |
| 109 | }; |
| 110 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 111 | const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 112 | { |
| 113 | /* Type 2 or Type 1 fused like Type 2. */ |
Felix Held | 42b0e8f | 2020-06-26 18:03:53 +0200 | [diff] [blame] | 114 | if (soc_is_reduced_io_sku()) { |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 115 | *num = ARRAY_SIZE(dali_dxio_descriptors); |
| 116 | return dali_dxio_descriptors; |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 117 | } else { |
| 118 | /* Type 1 */ |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 119 | *num = ARRAY_SIZE(pco_dxio_descriptors); |
| 120 | return pco_dxio_descriptors; |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | } |
| 124 | |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 125 | static const fsp_ddi_descriptor pco_ddi_descriptors[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 126 | { |
| 127 | // DDI0, DP0, eDP |
| 128 | .connector_type = EDP, |
| 129 | .aux_index = AUX1, |
| 130 | .hdp_index = HDP1 |
| 131 | }, |
| 132 | { |
| 133 | // DDI1, DP1, DB OPT1 HDMI |
| 134 | .connector_type = HDMI, |
| 135 | .aux_index = AUX2, |
| 136 | .hdp_index = HDP2 |
| 137 | }, |
| 138 | { |
| 139 | // DDI2, DP2, DB OPT1 USB-C1 |
| 140 | .connector_type = DP, |
| 141 | .aux_index = AUX3, |
| 142 | .hdp_index = HDP3, |
| 143 | }, |
| 144 | { |
| 145 | // DDI3, DP3, USB-C0 |
| 146 | .connector_type = DP, |
| 147 | .aux_index = AUX4, |
| 148 | .hdp_index = HDP4, |
| 149 | } |
| 150 | }; |
| 151 | |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 152 | static const fsp_ddi_descriptor dali_ddi_descriptors[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 153 | { |
| 154 | // DDI0, DP0, eDP |
| 155 | .connector_type = EDP, |
| 156 | .aux_index = AUX1, |
| 157 | .hdp_index = HDP1 |
| 158 | }, |
| 159 | { |
| 160 | // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub |
| 161 | .connector_type = DP, |
| 162 | .aux_index = AUX2, |
| 163 | .hdp_index = HDP2 |
| 164 | }, |
| 165 | { |
| 166 | // DDI2, DP3, USB-C0 |
| 167 | .connector_type = DP, |
| 168 | .aux_index = AUX4, |
| 169 | .hdp_index = HDP4, |
| 170 | } |
| 171 | }; |
| 172 | |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 173 | const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 174 | { |
| 175 | /* Type 2 or Type 1 fused like Type 2. */ |
Felix Held | 42b0e8f | 2020-06-26 18:03:53 +0200 | [diff] [blame] | 176 | if (soc_is_reduced_io_sku()) { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 177 | *num = ARRAY_SIZE(dali_ddi_descriptors); |
| 178 | return dali_ddi_descriptors; |
| 179 | } else { |
| 180 | /* Type 1 */ |
| 181 | *num = ARRAY_SIZE(pco_ddi_descriptors); |
| 182 | return pco_ddi_descriptors; |
| 183 | } |
| 184 | } |