Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/variants.h> |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 4 | #include <delay.h> |
| 5 | #include <gpio.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 6 | #include <soc/smi.h> |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 7 | #include <variant/gpio.h> |
| 8 | |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 9 | static const struct soc_amd_gpio gpio_set_stage_ram[] = { |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 10 | /* PWR_BTN_L */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 11 | PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 12 | /* SYS_RESET_L */ |
| 13 | PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), |
Rob Barnes | d1095c7 | 2020-09-25 14:16:46 -0600 | [diff] [blame] | 14 | /* WIFI_PCIE_WAKE_ODL */ |
Felix Held | f8e440c | 2021-03-24 00:17:35 +0100 | [diff] [blame] | 15 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 16 | /* H1_FCH_INT_ODL */ |
| 17 | PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 18 | /* PEN_DETECT_ODL */ |
Furquan Shaikh | ffbf5d9 | 2020-06-30 14:07:46 -0700 | [diff] [blame] | 19 | PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 20 | /* PEN_POWER_EN - Enabled*/ |
| 21 | PAD_GPO(GPIO_5, HIGH), |
Furquan Shaikh | 462f3ed | 2020-06-18 01:44:21 -0700 | [diff] [blame] | 22 | /* EN_PWR_TOUCHPAD */ |
| 23 | PAD_GPO(GPIO_6, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 24 | /* I2S_SDIN */ |
| 25 | PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), |
| 26 | /* I2S_LRCLK - Bit banged in depthcharge */ |
| 27 | PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), |
| 28 | /* TOUCHPAD_INT_ODL */ |
Victor Ding | c82db71 | 2021-04-15 04:31:54 +0000 | [diff] [blame] | 29 | PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), |
Martin Roth | 6a62cc8 | 2020-12-02 16:37:58 -0700 | [diff] [blame] | 30 | /* S0iX SLP - goes to EC */ |
| 31 | PAD_GPO(GPIO_10, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 32 | /* EC_IN_RW_OD */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 33 | PAD_GPI(GPIO_11, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 34 | /* USI_INT_ODL */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 35 | PAD_GPI(GPIO_12, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 36 | /* GPIO_13 - GPIO_15: Not available */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 37 | /* USB_OC0_L - USB C0/A0 */ |
| 38 | PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 39 | /* USB_OC1_L - USB C1 */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 40 | PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 41 | /* WIFI_DISABLE */ |
| 42 | PAD_GPO(GPIO_18, LOW), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 43 | /* I2C3_SCL - H1 */ |
| 44 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 45 | /* I2C3_SDA - H1 */ |
| 46 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 47 | /* EMMC_CMD */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 48 | PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 49 | /* EC_FCH_SCI_ODL */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 50 | PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 51 | /* AC_PRES */ |
| 52 | PAD_NF(GPIO_23, AC_PRES, PULL_UP), |
Furquan Shaikh | 489ffef | 2020-06-30 14:08:27 -0700 | [diff] [blame] | 53 | /* EC_FCH_WAKE_L */ |
| 54 | PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 55 | /* GPIO_25: Not available */ |
| 56 | /* PCIE_RST0_L - Fixed timings */ |
| 57 | PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), |
| 58 | /* GPIO_27: Configured in bootblock. */ |
| 59 | /* GPIO_28: Not available */ |
| 60 | /* GPIO_29: Handled in bootblock for wifi power/reset control. */ |
| 61 | /* FCH_ESPI_EC_CS_L */ |
| 62 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 63 | /* EC_AP_INT_ODL (Sensor Framesync) */ |
| 64 | PAD_GPI(GPIO_31, PULL_NONE), |
Furquan Shaikh | 5474f8e | 2020-08-05 14:54:39 -0700 | [diff] [blame] | 65 | /* EN_PWR_TOUCHSCREEN */ |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 66 | PAD_GPO(GPIO_32, HIGH), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 67 | /* GPIO_33 - GPIO_39: Not available */ |
| 68 | /* NVME_AUX_RESET_L */ |
| 69 | PAD_GPO(GPIO_40, HIGH), |
| 70 | /* GPIO_41: Not available */ |
| 71 | /* GPIO_42: Handled in bootblock for wifi power/reset control. */ |
| 72 | /* GPIO_43 - GPIO_66: Not available */ |
Furquan Shaikh | 462f3ed | 2020-06-18 01:44:21 -0700 | [diff] [blame] | 73 | /* DMIC_SEL */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 74 | /* |
Furquan Shaikh | 462f3ed | 2020-06-18 01:44:21 -0700 | [diff] [blame] | 75 | * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash |
| 76 | * access will be very slow. |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 77 | */ |
Furquan Shaikh | 462f3ed | 2020-06-18 01:44:21 -0700 | [diff] [blame] | 78 | PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic |
Kevin Chiu | 768f59a | 2020-09-26 20:34:28 +0800 | [diff] [blame] | 79 | /* EMMC_RESET_L */ |
| 80 | PAD_GPO(GPIO_68, HIGH), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 81 | /* RAM ID 3 */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 82 | PAD_GPI(GPIO_69, PULL_NONE), |
| 83 | /* EMMC_CLK */ |
| 84 | PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 85 | /* GPIO_71 - GPIO_73: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 86 | /* EMMC_DATA4 */ |
| 87 | PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), |
| 88 | /* EMMC_DATA6 */ |
| 89 | PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), |
| 90 | /* EN_PWR_CAMERA */ |
| 91 | PAD_GPO(GPIO_76, HIGH), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 92 | /* GPIO_77 - GPIO_83: Not available */ |
Josie Nordrum | cc72e15 | 2020-08-03 11:39:41 -0600 | [diff] [blame] | 93 | /* HP_INT_ODL */ |
| 94 | PAD_GPI(GPIO_84, PULL_NONE), |
Chris Wang | ad481c4 | 2020-12-01 17:14:17 +0800 | [diff] [blame] | 95 | /* APU_EDP_BL_DISABLE */ |
| 96 | PAD_GPO(GPIO_85, LOW), |
Martin Roth | 11c765c | 2020-11-17 09:55:58 -0700 | [diff] [blame] | 97 | /* RAM ID 2 - Keep High */ |
| 98 | PAD_GPO(GPIO_86, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 99 | /* EMMC_DATA7 */ |
| 100 | PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), |
| 101 | /* EMMC_DATA5 */ |
| 102 | PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), |
Furquan Shaikh | 79dba4a | 2020-08-04 17:16:33 -0700 | [diff] [blame] | 103 | /* GPIO_89 - unused */ |
| 104 | PAD_NC(GPIO_89), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 105 | /* RAM ID 1 */ |
| 106 | PAD_GPI(GPIO_90, PULL_NONE), |
Furquan Shaikh | 7f892b5 | 2020-07-21 22:54:16 -0700 | [diff] [blame] | 107 | /* EN_SPKR */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 108 | PAD_GPO(GPIO_91, LOW), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 109 | /* CLK_REQ0_L - WIFI */ |
| 110 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
| 111 | /* GPIO_93 - GPIO_103: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 112 | /* EMMC_DATA0 */ |
| 113 | PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), |
| 114 | /* EMMC_DATA1 */ |
| 115 | PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), |
| 116 | /* EMMC_DATA2 */ |
| 117 | PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), |
| 118 | /* EMMC_DATA3 */ |
| 119 | PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 120 | /* ESPI_ALERT_L */ |
| 121 | PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 122 | /* EMMC_DS */ |
| 123 | PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 124 | /* GPIO_110 - GPIO112: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 125 | /* I2C2_SCL - USI/Touchpad */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 126 | PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 127 | /* I2C2_SDA - USI/Touchpad */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 128 | PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 129 | /* CLK_REQ1_L - SD Card */ |
| 130 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
| 131 | /* CLK_REQ2_L - NVMe */ |
| 132 | PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), |
| 133 | /* GPIO_117 - GPIO_128: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 134 | /* KBRST_L */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 135 | PAD_NF(GPIO_129, KBRST_L, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 136 | /* GPIO_130 - GPIO_131: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 137 | /* RAM ID 0 */ |
| 138 | PAD_GPI(GPIO_132, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 139 | /* GPIO_133 - GPIO_134: Not available */ |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 140 | /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ |
| 141 | PAD_GPI(GPIO_135, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 142 | /* UART0_RXD - DEBUG */ |
| 143 | PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), |
Furquan Shaikh | ca36acf | 2020-07-03 10:32:41 -0700 | [diff] [blame] | 144 | /* BIOS_FLASH_WP_ODL */ |
| 145 | PAD_GPI(GPIO_137, PULL_NONE), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 146 | /* UART0_TXD - DEBUG */ |
| 147 | PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 148 | /* DEV_BEEP_BCLK */ |
| 149 | PAD_GPI(GPIO_139, PULL_NONE), |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 150 | /* TOUCHSCREEN_RESET_L */ |
| 151 | PAD_GPO(GPIO_140, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 152 | /* USB_HUB_RST_L */ |
| 153 | PAD_GPO(GPIO_141, HIGH), |
Furquan Shaikh | fd4fbe8 | 2020-07-21 22:29:49 -0700 | [diff] [blame] | 154 | /* SD_AUX_RESET_L */ |
| 155 | PAD_GPO(GPIO_142, HIGH), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 156 | /* BT_DISABLE */ |
| 157 | PAD_GPO(GPIO_143, LOW), |
Furquan Shaikh | dcee4b6 | 2020-07-22 00:47:40 -0700 | [diff] [blame] | 158 | /* USI_REPORT_EN */ |
| 159 | PAD_GPO(GPIO_144, LOW), |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 160 | }; |
| 161 | |
Matt DeVillier | 4a16be9 | 2022-09-23 13:36:36 -0500 | [diff] [blame] | 162 | const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) |
Raul E Rangel | b3c4132 | 2020-05-20 14:07:41 -0600 | [diff] [blame] | 163 | { |
| 164 | *size = ARRAY_SIZE(gpio_set_stage_ram); |
| 165 | return gpio_set_stage_ram; |
| 166 | } |
| 167 | |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 168 | static void wifi_power_reset_configure_active_low_power(void) |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 169 | { |
| 170 | /* |
| 171 | * Configure WiFi GPIOs such that: |
| 172 | * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device. |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 173 | * - Enable power to WiFi using EN_PWR_WIFI_L. |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 174 | * - Wait for 50ms after power to WiFi is enabled. |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 175 | * - Deassert WIFI_AUX_RESET. |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 176 | */ |
| 177 | static const struct soc_amd_gpio v3_wifi_table[] = { |
| 178 | /* WIFI_AUX_RESET */ |
| 179 | PAD_GPO(GPIO_29, HIGH), |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 180 | /* EN_PWR_WIFI_L */ |
| 181 | PAD_GPO(GPIO_42, LOW), |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 182 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 183 | gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 184 | |
| 185 | mdelay(50); |
| 186 | gpio_set(GPIO_29, 0); |
| 187 | } |
| 188 | |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 189 | static void wifi_power_reset_configure_active_high_power(void) |
| 190 | { |
| 191 | /* |
| 192 | * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET |
| 193 | * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be |
| 194 | * set low before driving it high to trigger a WiFi power cycle to meet PCIe |
| 195 | * requirements. Thus, configure GPIOs such that: |
| 196 | * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device |
| 197 | * - Disable power to WiFi. |
| 198 | * - Wait 10ms for WiFi power to go low. |
| 199 | * - Enable power to WiFi using EN_PWR_WIFI. |
| 200 | * - Deassert WIFI_AUX_RESET. |
| 201 | */ |
| 202 | static const struct soc_amd_gpio v3_wifi_table[] = { |
| 203 | /* WIFI_AUX_RESET */ |
| 204 | PAD_GPO(GPIO_29, HIGH), |
| 205 | /* EN_PWR_WIFI */ |
| 206 | PAD_GPO(GPIO_42, LOW), |
| 207 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 208 | gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 209 | |
| 210 | mdelay(10); |
| 211 | gpio_set(GPIO_42, 1); |
| 212 | mdelay(50); |
| 213 | gpio_set(GPIO_29, 0); |
| 214 | } |
| 215 | |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 216 | static void wifi_power_reset_configure_v3(void) |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 217 | { |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 218 | if (variant_has_active_low_wifi_power()) |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 219 | wifi_power_reset_configure_active_low_power(); |
| 220 | else |
| 221 | wifi_power_reset_configure_active_high_power(); |
| 222 | } |
| 223 | |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 224 | static void wifi_power_reset_configure_pre_v3(void) |
| 225 | { |
| 226 | /* |
| 227 | * Configure WiFi GPIOs such that: |
| 228 | * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. |
| 229 | * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# |
| 230 | * deassertion causing WiFi to enter a bad state. |
| 231 | * - Wait 10ms for WiFi power to go low. |
| 232 | * - Enable power to WiFi using EN_PWR_WIFI. |
| 233 | * - Wait for 50ms after power to WiFi is enabled. |
| 234 | * - Deassert WIFI_AUX_RESET_L. |
| 235 | */ |
| 236 | static const struct soc_amd_gpio pre_v3_wifi_table[] = { |
| 237 | /* WIFI_AUX_RESET_L */ |
| 238 | PAD_GPO(GPIO_42, LOW), |
| 239 | /* EN_PWR_WIFI */ |
| 240 | PAD_GPO(GPIO_29, LOW), |
| 241 | }; |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 242 | gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 243 | |
| 244 | mdelay(10); |
| 245 | gpio_set(GPIO_29, 1); |
| 246 | mdelay(50); |
| 247 | gpio_set(GPIO_42, 1); |
| 248 | } |
| 249 | |
Matt DeVillier | bfad0b0 | 2022-11-11 10:56:07 -0600 | [diff] [blame] | 250 | void baseboard_pcie_gpio_configure(void) |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 251 | { |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 252 | static const struct soc_amd_gpio pcie_gpio_table[] = { |
| 253 | /* PCIE_RST1_L - Variable timings (May remove) */ |
| 254 | PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), |
| 255 | /* NVME_AUX_RESET_L */ |
| 256 | PAD_GPO(GPIO_40, HIGH), |
| 257 | /* CLK_REQ0_L - WIFI */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 258 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 259 | /* CLK_REQ1_L - SD Card */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 260 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 261 | /* CLK_REQ2_L - NVMe */ |
Furquan Shaikh | dce0ce9 | 2020-07-17 11:16:50 -0700 | [diff] [blame] | 262 | PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 263 | /* SD_AUX_RESET_L */ |
| 264 | PAD_GPO(GPIO_142, HIGH), |
| 265 | }; |
| 266 | |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 267 | gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); |
Furquan Shaikh | 56f949c | 2020-07-15 13:58:59 -0700 | [diff] [blame] | 268 | |
Furquan Shaikh | 9f47a05 | 2020-06-24 00:03:06 -0700 | [diff] [blame] | 269 | /* Deassert PCIE_RST1_L */ |
| 270 | gpio_set(GPIO_27, 1); |
| 271 | |
Furquan Shaikh | 30ee0d8 | 2020-07-07 12:50:55 -0700 | [diff] [blame] | 272 | if (variant_uses_v3_schematics()) |
| 273 | wifi_power_reset_configure_v3(); |
Furquan Shaikh | 8302585 | 2020-06-22 10:45:12 -0700 | [diff] [blame] | 274 | else |
| 275 | wifi_power_reset_configure_pre_v3(); |
| 276 | } |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 277 | |
Martin Roth | 726504a | 2020-10-30 16:41:32 -0600 | [diff] [blame] | 278 | __weak void finalize_gpios(int slp_typ) |
| 279 | { |
| 280 | } |
| 281 | |
| 282 | const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) |
| 283 | { |
| 284 | *size = 0; |
| 285 | return NULL; |
| 286 | } |
| 287 | |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 288 | static const struct soc_amd_gpio gpio_sleep_table[] = { |
Martin Roth | 6a62cc8 | 2020-12-02 16:37:58 -0700 | [diff] [blame] | 289 | /* S0iX SLP */ |
| 290 | PAD_GPO(GPIO_10, LOW), |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 291 | /* PCIE_RST1_L */ |
| 292 | PAD_GPO(GPIO_27, LOW), |
Furquan Shaikh | 70b7fa1 | 2020-06-29 11:56:04 -0700 | [diff] [blame] | 293 | /* |
| 294 | * On pre-v3 schematics, GPIO_29 is EN_PWR_WIFI. So, setting to high should be no-op. |
| 295 | * On v3+ schematics, GPIO_29 is WIFI_AUX_RESET. Setting to high ensures that PERST# is |
| 296 | * asserted to WiFi device until coreboot reconfigures GPIO_29 on resume path. |
| 297 | */ |
| 298 | PAD_GPO(GPIO_29, HIGH), |
Furquan Shaikh | 189a5c7 | 2020-06-29 18:50:50 -0700 | [diff] [blame] | 299 | /* NVME_AUX_RESET_L */ |
| 300 | PAD_GPO(GPIO_40, LOW), |
| 301 | /* EN_PWR_CAMERA */ |
| 302 | PAD_GPO(GPIO_76, LOW), |
| 303 | }; |
| 304 | |
| 305 | const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) |
| 306 | { |
| 307 | *size = ARRAY_SIZE(gpio_sleep_table); |
| 308 | return gpio_sleep_table; |
| 309 | } |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 310 | |
Raul E Rangel | 04cf427 | 2021-12-06 12:15:45 -0700 | [diff] [blame] | 311 | static const struct soc_amd_gpio espi_gpio_table[] = { |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 312 | /* PCIE_RST0_L - Fixed timings */ |
| 313 | PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), |
| 314 | /* FCH_ESPI_EC_CS_L */ |
| 315 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
| 316 | /* ESPI_ALERT_L */ |
| 317 | PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), |
Raul E Rangel | 04cf427 | 2021-12-06 12:15:45 -0700 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) |
| 321 | { |
| 322 | *size = ARRAY_SIZE(espi_gpio_table); |
| 323 | return espi_gpio_table; |
| 324 | } |
| 325 | |
| 326 | static const struct soc_amd_gpio tpm_gpio_table[] = { |
| 327 | /* H1_FCH_INT_ODL */ |
| 328 | PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), |
| 329 | /* I2C3_SCL - H1 */ |
| 330 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 331 | /* I2C3_SDA - H1 */ |
| 332 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
| 333 | /* EC_IN_RW_OD */ |
| 334 | PAD_GPI(GPIO_11, PULL_NONE), |
| 335 | }; |
| 336 | |
| 337 | const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) |
| 338 | { |
| 339 | *size = ARRAY_SIZE(tpm_gpio_table); |
| 340 | return tpm_gpio_table; |
| 341 | } |
| 342 | |
| 343 | static const struct soc_amd_gpio early_gpio_table[] = { |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 344 | /* UART0_RXD - DEBUG */ |
| 345 | PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), |
| 346 | /* UART0_TXD - DEBUG */ |
| 347 | PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) |
| 351 | { |
| 352 | *size = ARRAY_SIZE(early_gpio_table); |
| 353 | return early_gpio_table; |
| 354 | } |
Matt DeVillier | c429ee1 | 2022-11-11 16:14:33 -0600 | [diff] [blame] | 355 | |
Matt DeVillier | 6da5e0b | 2022-11-11 14:59:50 -0600 | [diff] [blame] | 356 | static const struct soc_amd_gpio romstage_gpio_table[] = { |
| 357 | /* Enable touchscreen, hold in reset */ |
| 358 | /* EN_PWR_TOUCHSCREEN */ |
| 359 | PAD_GPO(GPIO_32, HIGH), |
| 360 | /* TOUCHSCREEN_RESET_L */ |
| 361 | PAD_GPO(GPIO_140, LOW), |
| 362 | }; |
Matt DeVillier | c429ee1 | 2022-11-11 16:14:33 -0600 | [diff] [blame] | 363 | |
| 364 | const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) |
| 365 | { |
| 366 | *size = ARRAY_SIZE(romstage_gpio_table); |
| 367 | return romstage_gpio_table; |
| 368 | } |